PCI JTAG Bug, 7/25/01

It was discovered that many modern PCs do not operate the PCI JTAG lines in
the manner anticipated in 1996.  This has been found to cause SP ASIC to 
behave incorrectly, in turn causing the RLP to behave incorrectly.  The
remedy involves eliminating the PCI JTAG feature from the RLP as follows.

1.  Remove PCI board-edge connector P1 pads A1 (TRST), A3 (TMS), B2 (TCK),
and B4 (TDO), or if they do not contain vias, cut the traces from them as
close to the pads as possible.

2.  Wire PIFS ASIC U5 pins 144 (TMS) and 140 (VCC) together.

3.  Wire PIFS ASIC U5 pin 145 (TCK) to PBC ASIC U8 pin 156 (SCL).

4.  Wire PIFS ASIC U5 pins 146 (TRST) and 142 (GND) together.

--Ken Winiecki