RLP PCI Card Rev. "-": Programming the FIFO Flags Ken Winiecki 1/17/98 INTRODUCTION The following information pertains to setting the programmable almost-full and almost-empty flag offsets ("PAEFO" and "PAFFO") of the IDT72271 byte-wide, 32- kB-deep FIFO memory devices used on the RLP PCI Card Rev. "-". Determining the offset values is discussed in the Return Link Processor PCI Card, Revision "-", Hardware Definition Document, section 5.3.11. SETUP & DEFAULTS For the flags to be programmable in the first place, the Universal FIFO Load signal (Baseboard Interface Control register $040000 bit 6) MUST be in the asserted state (0) WHENEVER ANY of the applicable Master Reset signals (Baseboard Interface Control register $040000 bits 13, 15, 18, 21) transition from asserted to deasserted (0 to 1). Under this condition the PAEFO and PAFFO default to $07F. This means that the PAEF will deassert (possibly triggering an interrupt) when the amount of data in the 32-kB-deep device rises to 128 bytes (a total of 512 bytes in the 4- device Transfer FIFO), and the PAFF asserts (possibly triggering an interrupt) when the amount of data in a device rises to 32,641 bytes (a total of 130,564 bytes in the 4-device Transfer FIFO). This is not to be confused with the FS-to-RS and RS-to-SP FIFOs which are different, IDT72265 16-bit-wide 32-kB-deep FIFO memory devices. Also, their Load signals are hardwired deasserted, so their flags are not programmable, and their PAEFOs and PAFFOs default to $3FF (words). This means that the PAEF will deassert (possibly triggering an interrupt) when the amount of data in a device rises to 2,048 bytes, and the PAFF asserts (possibly triggering an interrupt) when the amount of data in a device rises to 30,722 bytes. PROGRAMMING The RLP contains 17 byte-wide, 32-kB-deep FIFO devices. 13 of them are "Data" FIFOs: 12 buffer byte-wide telemetry data output from the SP Chip (in SP Mode), RS Chip (in RS-Direct Mode), PIFS Chip (in FS-Direct Mode), and one buffers byte-wide status data output from the Status Collector. The remaining four are wired in parallel to form the "Transfer" FIFO to buffer data from the 13 Data FIFOs in 32-bit words for transfer across the PCI bus. Each FIFO device contains 4 byte-wide programmable offset registers which are filled sequentially from the FIFO data input port, and read sequentially from the FIFO data output port, when the Universal FIFO Load signal (Baseboard Interface Control register $040000 bit 6) is asserted (0). Note since the read and write pointers to the offset registers are internal to the device and inaccessible, the only safe course of action is to always read and write all four registers at a time. The first offset register pair forms the 15-bit PAEFO and the second pair forms the 15-bit PAFFO. In particular, bits 7-0 of byte 1 are bits 7-0 of the PAEFO, bits 6-0 of byte 2 are bits 15-8 of the PAEFO, bits 7-0 of byte 3 are bits 7-0 of the PAFFO, and bits 6-0 of byte 4 are bits 15-8 of the PAFFO; other bits don't matter. The input and output ports of most of the FIFOs are aliased over large tracts of contiguous addresses so that sequential reads and writes to sequential locations act the same as sequential reads and writes to a single location. Such ports respond to data bits 8-0, so since all RLP accesses must be 32-bit, bits 31-9 are ignored. The four parallel devices of the Transfer FIFO are controlled such that all of them simultaneously receive whatever is written (once) to Transfer FIFO input space. As such, writing and reading most offsets are extremely straightforward. Warning: telemetry and status data cannot be flowing while programming the FIFO flags; any such data being written by an upstream device will go into the offset registers and be lost, and any reads performed by the downstream device on the FIFO will receive the contents of the offset registers instead of telemetry or status data. For the Status Data FIFO, say we wish to collect so much frame and/or packet status that servicing the FIFO with the Status Collection Done indicator once per status request becomes impractical. Board logic uses the almost-full flag, so we "leave" (actually reprogram) that to its default state and reprogram the almost-empty flag to use as an interrupt source. Remembering that data transfers must be an integral number of 4-byte words, say we decide to service status data in 4 kB ($1000 B) blocks. This is achieved with a PAEFO of $0FFF. The Status Data FIFO Input Space starts at $108000, so the programming sequence looks like: Action Address Data Description ------ -------- ---------- ------------------------------------------- write 0x040000 0x003FFF86 assert Load (among other things) write 0x108000 0x000000FF Status Data FIFO PAEFO[07-00]=$FF write 0x108004 0x0000000F Status Data FIFO PAEFO[15-08]=$0F write 0x108008 0x0000007F Status Data FIFO PAFFO[07-00]=$7F (default) write 0x10800C 0x00000000 Status Data FIFO PAFFO[15-08]=$00 (default) write 0x040000 0x003FFFC6 deassert Load (among other things) Reading the Status Data FIFO programmable flag offsets is almost as simple. The Data FIFO output space is controlled by the DMA Interface, so the Status Data FIFO must be selected first using DMA Interface Channel A Control register $0A0000 bits 20-17. The Data FIFO output space starts at $0C0000, so the programming sequence looks like: Action Address Data Description ------ -------- ---------- ------------------------------------------- write 0x0A0000 0x00180000 select Status Data FIFO write 0x040000 0x003FFF86 assert Load (among other things) read 0x0C0000 [07-00]==Data FIFO PEAFO[07-00] read 0x0C0004 [06-00]==Data FIFO PEAFO[15-08] read 0x0C0008 [07-00]==Data FIFO PAFFO[07-00] read 0x0C000C [06-00]==Data FIFO PAFFO[15-08] write 0x040000 0x003FFFC6 deassert Load (among other things) For the DMA Interface Transfer FIFO, programming and reading the flag offsets is very similar to that of the Status Data FIFO. The addresses are different: the Transfer FIFO input space begins at $0E0000, and the output space begins at $080000. There is no need to select a Data FIFO for reading. Again, the almost-full flag is used by the board logic and so should always be reprogrammed to the default. The almost-empty flag is not useful as an interrupt source, and is used by the board logic to control bursting of data across the local bus (and hence the PCI bus), BUT THIS MUST ALWAYS BE SET TO ZERO because the PCI Bridge Chip does its own PCI and local bus bursting, and so setting it to anything else WILL reduce performance. Note that the offset entered applies to 4 FIFO devices, so the total number of bytes accumulated for a burst is equal to 4 times what is indicated by an individual offset. Also note that all 4 FIFO devices output to different bytes of the 32-bit Transfer FIFO output space, so a single read should contain four identical values (since the 4 FIFO devices were identically programmed). For the 12 SP Data FIFOs, programming the flag offsets is more complex. The offset register values are determined the exact same way as the Status Data FIFO, but they cannot be written directly to the FIFOs, they must be written to SP memory which must then be dumped out to the FIFO(s). The SP's ability to write to any combination of FIFOs can be used to program different SP Data FIFOs with different flag offsets. The programming sequence could look something like this (no guarantees): Action Address Data Description ------ -------- ---------- ------------------------------------------- write 0x1????? 0x000000FF SP mem: Data FIFO PEAFO[07-00]=$FF write 0x1????? 0x0000000F SP mem: Data FIFO PEAFO[15-08]=$0F write 0x1????? 0x0000007F SP mem: Data FIFO PAFFO[07-00]=$7F (default) write 0x1????? 0x00000000 SP mem: Data FIFO PAFFO[15-08]=$00 (default) write 0x040000 0x003FFF86 assert Load (among other things) write 0x1????? 0x???????? tell SP to dump SP mem to Data FIFO(s) write 0x040000 0x003FFFC6 deassert Load (among other things) Reading the SP Data FIFO programmable flag offsets is much simpler; it is exactly the same as reading that of the Status Data FIFO. Only a different FIFO is selected with the DMA Interface Channel A Control register. One SP Data FIFO, the one used by RS-Direct and FS-Direct modes, can also be programmed through the PIFS chip. This is only worth the effort when the SP chip is malfunctioning or absent, since otherwise the other 11 SP Data FIFOs will be programmed through the SP. In this case, the RLP is operated in FS- Direct Mode (Baseboard Interface Control register $040000 bits 4-3 set to 01, PIFS chip set for 8-bit output). Additionally, the PIFS must be set up to pass CPU Data and not append anything. The PIFS CPU Data register only passes data bits [31..24]. Other than that, the programming sequence looks similar to that of the Status Data FIFO: Action Address Data Description ------ -------- ---------- ------------------------------------------- write 0x1100?? 0x???????? PIFS: 8-bit out, CPU Data in, no trailer... write 0x040000 0x003FFF8E assert Load, select FS-Direct, etc. write 0x108000 0xFF000000 Misc Data FIFO PEAFO[07-00]=$FF write 0x108004 0x0F000000 Misc Data FIFO PEAFO[15-08]=$0F write 0x108008 0x7F000000 Misc Data FIFO PAFFO[07-00]=$7F (default) write 0x10800C 0x00000000 Misc Data FIFO PAFFO[15-08]=$00 (default) write 0x040000 0x003FFFCE deassert Load (among other things) Happy return-link-processing!