Return Link Processing PCI Card Revision "-" Memory Map Note: only longword accesses are supported. 000000- DMA-chaining memory space, 256 KB 03FFFF 000000- DMA-chaining memory, 128 KB (32 KLW) 01FFFF 020000- unused (aliased DMA-chaining memory), 128 KB 03FFFF 040000- baseboard interface space, 256 KB 07FFFF 040000- baseboard interface register space, 32 B (8 LW), 04001F 5 LW registers actually used (40 B) 040000 control register, read/write, post-reset value 0x85 [31-25] 0 (unused) [24] interrupt signal status mode (0=raw, 1=masked deasserted) [23] unused control signal [22] reset OSM (0=reset, 1=normal) [21] reset DMAI transfer FIFO (master) (0=reset, 1=normal) [20] reset DMAI (0=reset, 1=normal) [19] reset SC FIFO (partial) (0=reset, 1=normal) [18] reset SC FIFO (master) (0=reset, 1=normal) [17] reset SC (0=reset, 1=normal) [16] reset SP packet service FIFOs (partial) (0=reset, 1=normal) [15] reset SP packet service FIFOs (master) (0=reset, 1=normal) [14] reset SP frame service FIFOs (partial) (0=reset, 1=normal) [13] reset SP frame service FIFOs (master) (0=reset, 1=normal) [12] reset SP (0=reset, 1=normal) [11] reset RS-to-SP FIFO (0=reset, 1=normal) [10] reset RS (0=reset, 1=normal) [09] reset PIFS-to-RS FIFO (0=reset, 1=normal) [08] reset PIFS (0=reset, 1=normal) [07] reset ECL serial-to-parallel converter (1=reset, 0=normal) [06] programmable flag load (0=load, 1=normal) [05] timecode reference clock select (0=internal, 1=external) [04-03] processing mode (00=SP, 01=PIFS-direct, 10=SP, 11=RS-direct) [02] ECL input select (0=single-ended, 1=differential) [01] LED control (0=on, 1=off) [00] clear overflow condition (1=clear, 0=normal) 040004 FIFO flag mask register A, read/write, post-reset value 0 [31] master interrupt enable (1=enable, 0=disable) [30] mask overflow condition (0=mask, 1=use) [29] mask SP status FIFO almost empty flag (0=mask, 1=use) [28] mask SP frame reject FIFO almost empty flag (0=mask, 1=use) [27] mask SP bitstream service FIFO almost empty flag (0=mask, 1=use) [26] mask SP (dynamic) frame service 3 / PIFS-direct / RS-direct FIFO almost empty flag (0=mask, 1=use) [25] mask SP (dynamic) frame service 2 FIFO almost empty flag (0=mask, 1=use) [24] mask SP (dynamic) frame service 1 FIFO almost empty flag (0=mask, 1=use) [23] mask SP static frame service 3 FIFO almost empty flag (0=mask, 1=use) [22] mask SP static frane service 2 FIFO almost empty flag (0=mask, 1=use) [21] mask SP static frame service 1 FIFO almost empty flag (0=mask, 1=use) [20] mask SP packet reject FIFO almost empty flag (0=mask, 1=use) [19] mask SP packet service 3 FIFO almost empty flag (0=mask, 1=use) [18] mask SP packet service 2 FIFO almost empty flag (0=mask, 1=use) [17] mask SP packet service 1 FIFO almost empty flag (0=mask, 1=use) [16] mask SP status FIFO almost full flag (0=mask, 1=use) [15] mask SP frame reject FIFO almost full flag (0=mask, 1=use) [14] mask SP bitstream service FIFO almost full flag (0=mask, 1=use) [13] mask SP (dynamic) frame service 3 / PIFS-direct / RS-direct FIFO almost full flag (0=mask, 1=use) [12] mask SP (dynamic) frame service 2 FIFO almost full flag (0=mask, 1=use) [11] mask SP (dynamic) frame service 1 FIFO almost full flag (0=mask, 1=use) [10] mask SP static frame service 3 FIFO almost full flag (0=mask, 1=use) [09] mask SP static frame service 2 FIFO almost full flag (0=mask, 1=use) [08] mask SP static frame service 1 FIFO almost full flag (0=mask, 1=use) [07] mask SP packet reject FIFO almost full flag (0=mask, 1=use) [06] mask SP packet service 3 FIFO almost full flag (0=mask, 1=use) [05] mask SP packet service 2 FIFO almost full flag (0=mask, 1=use) [04] mask SP packet service 1 FIFO almost full flag (0=mask, 1=use) [03] mask DMAI transfer FIFO full flag (0=mask, 1=use) [02] mask RS-to-SP FIFO full flag (0=mask, 1=use) [01] mask PIFS-to-RS FIFO full flag (0=mask, 1=use) [00] OSM interrupt signal mask (0=mask, 1=use) 040008 FIFO flag mask register B, read/write, post-reset value 0 [31-23] 0 (unused) [22] mask SC done signal (0=mask, 1=use) [21] mask SP status FIFO empty flag (0=mask, 1=use) [20] mask SP frame reject FIFO empty flag (0=mask, 1=use) [19] mask SP bitstream service FIFO empty flag (0=mask, 1=use) [18] mask SP (dynamic) frame service 3 / PIFS-direct / RS-direct FIFO empty flag (0=mask, 1=use) [17] mask SP (dynamic) frame service 2 FIFO empty flag (0=mask, 1=use) [16] mask SP (dynamic) frame service 1 FIFO empty flag (0=mask, 1=use) [15] mask SP static frame service 3 FIFO empty flag (0=mask, 1=use) [14] mask SP static frame service 2 FIFO empty flag (0=mask, 1=use) [13] mask SP static frame service 1 FIFO empty flag (0=mask, 1=use) [12] mask SP packet reject FIFO empty flag (0=mask, 1=use) [11] mask SP packet service 3 FIFO empty flag (0=mask, 1=use) [10] mask SP packet service 2 FIFO empty flag (0=mask, 1=use) [09] mask SP packet service 1 FIFO empty flag (0=mask, 1=use) [08] mask DMAI transfer FIFO empty flag (0=mask, 1=use) [07] mask RS-to-SP FIFO empty flag (0=mask, 1=use) [06] mask PIFS-to-RS FIFO empty flag (0=mask, 1=use) [05] mask DMAI transfer FIFO half full flag (0=mask, 1=use) [04] mask RS-to-SP FIFO half full flag (0=mask, 1=use) [03] mask PIFS-to-RS FIFO half full flag (0=mask, 1=use) [02] mask DMAI transfer FIFO almost full flag (0=mask, 1=use) [01] mask RS-to-SP FIFO almost full flag (0=mask, 1=use) [00] mask PIFS-to-RS FIFO almost full flag (0=mask, 1=use) 04000C FIFO flag register A, read-only [31] 0 (unused) [30] overflow condition (1=overflow int) [29] SP status FIFO almost empty (1=not almost empty int) [28] SP frame reject FIFO almost empty (1=not almost empty int) [27] SP bitstream service FIFO almost empty (1=not almost empty int) [26] SP (dynamic) frame service 3 / PIFS-direct / RS-direct FIFO almost empty (1=not almost empty int) [25] SP (dynamic) frame service 2 FIFO almost empty (1=not almost empty int) [24] SP (dynamic) frame service 1 FIFO almost empty (1=not almost empty int) [23] SP static frame service 3 FIFO almost empty (1=not almost empty int) [22] SP static frame service 2 FIFO almost empty (1=not almost empty int) [21] SP static frame service 1 FIFO almost empty (1=not almost empty int) [20] SP packet reject FIFO almost empty (1=not almost empty int) [19] SP packet service 3 FIFO almost empty (1=not almost empty int) [18] SP packet service 2 FIFO almost empty (1=not almost empty int) [17] SP packet service 1 FIFO almost empty (1=not almost empty int) [16] SP status FIFO almost full (0=almost full int) [15] SP frame reject FIFO almost full (0=almost full int) [14] SP bitstream service FIFO almost full (0=almost full int) [13] SP (dynamic) frame service 3 / PIFS-direct / RS-direct FIFO almost full (0=almost full int) [12] SP (dynamic) frame service 2 FIFO almost full (0=almost full int) [11] SP (dynamic) frame service 1 FIFO almost full (0=almost full int) [10] SP static frame service 3 FIFO almost full (0=almost full int) [09] SP static frame service 2 FIFO almost full (0=almost full int) [08] SP static frame service 1 FIFO almost full (0=almost full int) [07] SP packet reject FIFO almost full (0=almost full int) [06] SP packet service 3 FIFO almost full (0=almost full int) [05] SP packet service 2 FIFO almost full (0=almost full int) [04] SP packet service 1 FIFO almost full (0=almost full int) [03] DMAI transfer FIFO full (0=full int) [02] RS-to-SP FIFO full (0=full int) [01] PIFS-to-RS FIFO full (0=full int) [00] OSM interrupt signal 040010 FIFO flag register B, read-only [31-24] 0 (unused) [23] OSM present (1=present, 0=absent) [22] SC done signal (1=done int) [21] SP status FIFO empty (1=not empty int) [20] SP frame reject FIFO empty (1=not empty int) [19] SP bitstream service FIFO empty (1=not empty int) [18] SP (dynamic) frame service 3 / PIFS-direct / RS-direct FIFO empty (1=not empty int) [17] SP (dynamic) frame service 2 FIFO empty (1=not empty int) [16] SP (dynamic) frame service 1 FIFO empty (1=not empty int) [15] SP static frame service 3 FIFO empty (1=not empty int) [14] SP static frame service 2 FIFO empty (1=not empty int) [13] SP static frame service 1 FIFO empty (1=not empty int) [12] SP packet reject FIFO empty (1=not empty int) [11] SP packet service 3 FIFO empty (1=not empty int) [10] SP packet service 2 FIFO empty (1=not empty int) [09] SP packet service 1 FIFO empty (1=not empty int) [08] DMAI transfer FIFO empty (1=not empty int) [07] RS-to-SP FIFO empty (1=not empty int) [06] PIFS-to-RS FIFO empty (1=not empty int) [05] DMAI transfer FIFO half full (0=half full int) [04] RS-to-SP FIFO half full (0=half full int) [03] PIFS-to-RS FIFO half full (0=half full int) [02] DMAI transfer FIFO almost full (0=almost full int) [01] RS-to-SP FIFO almost full (0=almost full int) [00] PIFS-to-RS FIFO almost full (0=almost full int) 040014- 0 (last 3 LW registers unused) 04001F 040020- unused (aliased baseboard interface registers), 262124 B 07FFFF 080000- DMA interface space, 512 KB 0FFFFF 080000- DMAI transfer FIFO output space, 128 KB (32 KLW) 09FFFF 0A0000- DMA interface register superspace, 128 KB 0BFFFF 0A0000- DMA interface register space, 32 B (8 LW), 0A001F 5 LW registers actually used (40 B) 0A0000 control register channel A (read/write) (post-reset value 0) [31-21] = 0 (unused) [20-17] = data FIFO selection: 0000 = SP Packet Service 1 0001 = SP Packet Service 2 0010 = SP Packet Service 3 0011 = SP Packet Reject Service 0100 = SP (Dynamic) Frame Service 1 0101 = SP (Dynamic) Frame Service 2 0110 = SP (Dynamic) Frame Service 3 / RS-Direct / FS-Direct 0111 = SP Static Frame Service 1 1000 = SP Static Frame Service 2 1001 = SP Static Frame Service 3 1010 = SP Bitstream Service 1011 = SP Frame Reject Service 1100 = Status 1101, 1110, 1111 = no FIFO selected [16-00] = byte tranfer size (remaining) in bytes 0A0004 control register channel B (read/write) (post-reset value 0) [31-21] = 0 (unused) [20-17] = data FIFO selection: 0000 = SP Packet Service 1 0001 = SP Packet Service 2 0010 = SP Packet Service 3 0011 = SP Packet Reject Service 0100 = SP (Dynamic) Frame Service 1 0101 = SP (Dynamic) Frame Service 2 0110 = SP (Dynamic) Frame Service 3 / RS-Direct / FS-Direct 0111 = SP Static Frame Service 1 1000 = SP Static Frame Service 2 1001 = SP Static Frame Service 3 1010 = SP Bitstream Service 1011 = SP Frame Reject Service 1100 = Status 1101, 1110, 1111 = no FIFO selected [16-00] = byte tranfer size (remaining) in bytes 0A0008 fill count register channel A (read only) [31-17] = 0 (unused) [16-00] = count of fill bytes in most recent byte transfer A 0A000C fill count register channel B (read only) [31-17] = 0 (unused) [16-00] = count of fill bytes in most recent byte transfer B 0A0010 control register (read/write) (post-reset value 0x2) [31-02] = 0 (unused) [01] 0 partially resets DMAI transfer FIFO [00] 0 selects first byte to D[31-24], 1 selects to D[07-00] 0A0014- 0 (last 3 LW registers unused) 0A001F 0A0020- unused (aliased DMA interface registers), 131064 B 0BFFFF 0C0000- data FIFO output space, 128 KB (32 KLW), 0DFFFF but each longword reads only one data FIFO byte (32 KB) 0E0000- DMAI transfer FIFO input space, 128 KB (32 KLW) 0FFFFF 100000- telemetry processing interface space, 1 MB 1FFFFF 100000- status collector space, 64 KB 10FFFF 100000- status collector register space, 32 B (8 LW), 10001F 2 LW registers actually used (8 B) 100000 status collector control register (read/write) (post-reset 0) [31-27] = 0 (unused) [26-13] number of 4-byte packet status half-records to collect - 1 [12] 1 to collect SP packet status memory data... [11-04] number of 16-byte frame status half-records to collect - 1 [03] 1 to collect SP frame status data... [02] 1 to collect SP register data (112 W, 224 B) [01] 1 to collect RS register data ( 40 W, 80 B) [00] 1 to collect PIFS register data ( 32 LW, 128 B) 100004 A/D converter register (read-only) [31-16] = 0 (unused) [15-08] = board temperature code: x 2.03 = degrees Celsius [07-00] = board power code: x .203 = Watts, or x .0406 = Amps 100008- 0 (last 6 LW registers unused) 10001C 100020- unused (aliased status collector registers), 32760 B 107FFF 108000 status FIFO input space, 32 KB (8 KLW) 10FFFF 110000- PIFS space, 64 KB 11FFFF 110000- PIFS register space, 128 B (32 LW), 11007F 32 LW registers actually used (128 B) 1100xx see PIFS HDD for individual registers 110080- unused (aliased PIFS registers), 65408 B 11FFFF 120000- RS register superspace, 64 KB 12FFFF 120000- RS register space, 256 B (64 LW), 1200FF 40 W registers actually used, unpacked one W per LW 1200xx see RS HDD for individual registers 1200A0- 0 (last 24 LW unused) 1200FF but each longword reads only one 16-bit register 120100- unused (aliased RS registers), 65280 B 12FFFF 130000- RS internal scratch memory, 64 KB (16 KLW), 13FFFF but each longword reads only one byte (16 KB) 140000- SP register superspace, 64 KB 14FFFF 140000- SP register space, 512 B (128 LW), 1401FF 112 W registers actually used, unpacked one W per LW 140xxx see SP HDD for individual registers 1401C0- 0 (last 16 LW unused) 1401FF 140200- unused (aliased SP registers), 65024 B 14FFFF 150000- SP frame status memory space, 64 KB 15FFFF 150000- SP external frame status memory, 16 KB (4 KLW), 153FFF but each longword reads only one memory byte (4 KB) 154000- unused (aliased SP frame status memory), 48 KB 15FFFF 160000- SP packet status memory space, 128 KB 17FFFF 160000- SP external packet status memory, 64 KB 16FFFF 170000- unused (aliased SP external packet status memory), 64 KB 17FFFF 180000- SP packet buffer memory space, 256 KB, 1BFFFF multiple B and W spaces unpacked one per LW, see SP HDD 1C0000- unused, 256 KB 1FFFFF 200000 start of optional sorting module space, size defined by OSM itself up to 254 MB