RLP PCI Configuration Ken Winiecki -- 12/29/97 Each register description below consists of the register offset, register name, SEEPROM (hardware) configuration value, and if applicable, driver (software) configuration value and notes. $00: PCI_VENDOR ROM: $C521: NASA GSFC If the PCI Vendor register is hardware-configured to $FFFF, the chip will autoconfigure it to $11B0, the vendor ID for V3 Corp. It will also autoconfigure PCI_DEVICE (below). I requested the PCI SIG to reserve $C521 for us in September 1996. To my knowledge Barbie never paid the $2000 PCI SIG fee to officially assign us this value, so this should be done as soon as possible. As of today the value remains unassigned and so is probably safe to use. $02: PCI_DEVICE ROM: $0000: reserved $0001: PCI1OFR $0002: RLP $0003: FLS $0004: DRX $0005: RLP+OSM If PCI_VENDOR (above) is hardware-configured to $FFFF, the chip will autoconfigure the PCI Device register to $0004, the device ID for the V962PBC. $04: PCI_CMD ROM: $0000: reset DRV: $0206: see text The PCI Command register must be hardware-configured to $0000, otherwise PC BIOS will crash. After BIOS is finished, the driver should read the register and check that bit 1 (Memory Access Enable) is set. If it is not, the driver should activate a fatal-error scenario. Otherwise, it should attempt to set bits 9 (Fast Back-To-Back Transfer Enable) and 2 (Bus Master Enable), and clear bit 0 (I/O Access Enable). All other bits should be left as BIOS configured them. The example value shown assumes BIOS did not set any other bits; if it had, the value would be different. $06: PCI_STAT ROM: $0080 The PCI Status register should be hardware-configured with bit 7 (Fast Back-To-Back Transfer Target Enable) set and all other bits cleared as shown. $08: PCI_CC_REV ROM: $FF00000x: reserved $FF00001x: rev. - $FF00002x: rev. A $FF00003x: rev. B (...) $FF0000Fx: rev. N If the board revision exceeds N, the board should be given a new PCI_DEVICE designation and the board user revision ID should start over. The chip autoconfigures the don't-care nybble to its stepping: $0 - V962PBC revision A, $1 - B0, $2 - B1, $3 - B2, $4 - C0 (recently renamed EPC360 revision A0). $0C: PCI_HDR_CFG ROM: $00000000: reset DRV: $0000FF00 The PCI Header Configuration register should be hardware-configured to $00000000 because that is what the textbooks seem to say PC BIOS requires. After BIOS is finished, the driver should attempt to set the Latency Timer field to $FF (maximum) and all other fields to zero as shown. This will also clear any cache cache line size, which should be zero. $10: PCI_IO_BASE ROM: $00000000: reset DRV: see text $14: PCI_BASE0 ROM: $00000000: reset DRV: see text $18: PCI_BASE1 ROM: $00000000: reset DRV: see text The Memory Base registers should be hardware-configured to $00000000 because that is what the textbooks seem to say PC BIOS requires. After BIOS is finished, the driver should attempt to clear bit 3 (Read Prefetch Enable), leaving all other bits as BIOS congfigured them. $2C: PCI_SUB_VENDOR ROM: $0000 $2E: PCI_SUB_ID ROM: $0000 $30: PCI_ROM ROM: $00000000 $3C: PCI_BPARAM ROM: $01FF01FF DRV: check The PCI Bus Parameter register should be harware-configured with bits 32-24 set to $01 (minimum Maximum Latency; $00 means disabled), bits 23-26 set to $FF (maximum Minimum Grant; $00 means disabled), bits 15-8 set to $01 (Interrupt Pin INTA), and bits 7-0 set to $FF (Interrupt Line unassigned) as shown. After BIOS is finished, the driver should read the register and check that bits 15-8 are still $01 (Interrupt Pin INTA) and that bits 7-0 are no longer $FF (Interrupt Line has been assigned). If either of these is not the case, the driver should activate a fatal-error scenario. $40: PCI_MAP0 ROM: $00000013 The PCI Map register 0 should be hardware-configured with bits 7-4 set to $1 (Aperture Size 2 MB), bit 1 set (PCI_BASE0 Register Enable), bit 0 set (Aperture 0 Enable), and all other bits cleared as shown. $44: PCI_MAP1 ROM: $00000000 $48: PCI_INT_STAT ROM: $03000000 The PCI Interrupt Status register should be hardware-configured with bits 25 and 24 set (clear DMA interrupts) and all other bits cleared as shown. $4C: PCI_INT_CFG ROM: $00020000 DRV: 0102000C: see text The PCI Interrupt Configuration register should be hardware-configured with bits 17-16 set to $2 (INTA Interrupt Mode Software-Cleared) and all other bits cleared as shown. After BIOS is finished, the driver should reset PCI_INT_STAT (above) to the same value it was hardware-configured to, and then should read it and make sure all interrupts remain untriggered. If this is not the case, the driver should activate a fatal-error scenario. Otherwise, it should go ahead and attempt to set PCI_INT_CFG bit 24 (DMA Channel 0 Interrupt Enable), bit 3 (INTD Input to INTA Output), and bit 2 (INTC Input to INTA Output), leaving all other bits unchanged. $54: LB_BASE0 ROM: $00000000 $58: LB_BASE1 ROM: $00000000 $5E: LB_MAP0 ROM: $0000 $62: LB_MAP1 ROM: $0000 $6E: LB_IO_BASE ROM: $0000 $70: FIFO_CFG ROM: $C080 The FIFO Configuration register should be hardware-configured to perform the largest PCI bursts, second-largest local bus bursts, and the simplest FIFO strategies. $72: FIFO_PRIORITY ROM: $1000 The FIFO Priority register should be hardware-configured with bit 12 set (PCI Read from Local Before PCI Write to Local) and all other bits cleared (Local Write to PCI Before Local Read from PCI, No Flushing). $74: FIFO_STAT ROM: $0505 The FIFO Status register is read-only, but it should read All Empty as shown most of the time, so might as well put the same value in the hardware configuration. $76: LB_ISTAT ROM: $00 $77: LB_IMASK ROM: $00 $78: SYSTEM ROM: $E000 The System register should be hardware-configured with bit 15 set (Reset Output Deasserted), bit 14 set (SYSTEM Register Locked), bit 13 set (SCL Function), and all other bits cleared. $7B: LB_CFG ROM: $60 DRV: $60 The Local Bus Configuration register should be hardware-configured with bits 6 and 5 set (Local Bus Timeout Longest -- note bit 6 has no effect in rev B2) and all other bits cleared. After BIOS is finished, the driver should reset it to the same value it was hardware-configured to, in case it did not come up as set.