A RECONFIGURABLE MULTIPROCESSOR ARCHITECTURE
                      AND ITS ARITHMETIC PERFORMANCE

                                A Thesis
                              Presented to
                         the Graduate School of
                           Clemson University

                         In Partial Fulfillment
                   of the Requirements for the Degree
                           Master of Science
                          Computer Engineering

                                   by
                         Kenneth B. Winiecki, Jr.
                              August 1994


                                ABSTRACT

	A word-wide processing element ("PE") based on an existing 1-bit-
wide design is developed for a high-performance, massively-parallel, 
rectangular-mesh-connected, globally-routed, reconfigurable, MSIMD 
computer architecture.  The PE can perform up to three operations per 
instruction cycle (one transfer and two Boolean), and an instruction can 
be executed in one clock cycle.  It can communicate with up to four 
other PEs and a global data router via three word-wide ports and two 
bit-wide ports.  Individual PE operation can be disabled by the 
controller and conditionally by the PE itself.  Carry-lookahead logic 
facilitates fast full-addition/subtraction, and variable-shift registers 
enable improved floating-point performance.  Configurations of PEs are 
developed to perform integer and floating-point arithmetic with various 
methods and degrees of parallelism.  Behavioral models of the PE and the 
configurations are developed in the Verilog hardware description 
language, and the performance of the configurations is observed.  It is 
found that the PE design facilitates significant parallelization of many 
arithmetic operations, thereby producing appreciable speedup.  The 
success of this research indicates that this PE design should be further 
considered for the basis of a high-performance computer architecture.