APPENDIX
// pe.v
// Verilog-XL behavioral models of a reconfigurable-processing element
// to be used as a submodule of a controlling system
// for Dr. W. B. Ligon, E&CE Dept., Clemson U., 1992-4
// by Ken Winiecki

module pe0 
  (p_clock, p_reset, p_instr, p_flags,
   n_in, s_in, e_in, w_in, r_in, 
   n_out, s_out, e_out, w_out, r_out,
   m_clock, m_write, m_addr, m_in, m_out,
   dump_reg, dump_mem);

parameter // defaults, should be overridden by instantiating module:
  ADDR_WIDTH  = 10,           //  width of PE memory address, in bits
  WORD_WIDTH  = 32,           //  width of PE word, in bits
  MEM_LENGTH  = 1024,         //  length of PE memory, in words
  PE_NAME     = "undefined";  //  name of PE for dump identification

input // (1 bit wide)
  p_clock, p_reset,     //  PE clock & reset, rising-edge triggered
  e_in, w_in,           //  east (lsb) & west (msb) communication
  m_clock,              //  PE memory clock for external access, rising-edge
  m_write,              //  PE memory read/write control for external access:
                        //    read = 0, write = 1
  dump_reg, dump_mem;   //  PE register & memory dump clocks, rising-edge
input  [ADDR_WIDTH-1:0] 
  m_addr;               //  PE memory address for external access
input  [WORD_WIDTH-1:0]
  n_in, s_in, r_in,     //  PE north & south & router (word) communication
  m_in;                 //  PE memory data for external access
input  [ADDR_WIDTH+32-1:0] 
  p_instr;              //  PE instruction (described below)
output // (1 bit wide)
  e_out, w_out;         //  east (lsb) & west (msb) communication
output [9:0] 
  p_flags;              //  PE flags (described below)
output [WORD_WIDTH-1:0] 
  n_out, s_out, r_out,  //  PE north & south & router (word) communication
  m_out;                //  PE memory data for external access

reg temp_dis; // (1 bit wide)
reg [9:0] p_flags;
reg [7:0] out_res, reg_res;
reg [WORD_WIDTH-1:0] mem[0:MEM_LENGTH-1],
                     regs[0:15],
                     in_1, in_2, out, m_out,
                     last_out, r_in2, r;
reg [WORD_WIDTH:0] temp;
wire e_out, w_out;
wire [WORD_WIDTH-1:0] east, west;
integer i, j, reg_dump_ct, mem_dump_ct, clock_ct;

//  PE instruction field definitions and content parameters:
`define  mem_addr p_instr[ADDR_WIDTH+32-1:32]
`define  mem_ctrl p_instr[31:30]
  parameter NO_OP = 2'b00,  //  no memory operation
            R_OUT = 2'b01,  //  read to memory at address from OUT register
            W_IN1 = 2'b10,  //  write from memory at address to IN1 register
            W_IN2 = 2'b11;  //  write from memory at address to IN2 register
`define  dest_reg p_instr[29:26]
`define  srce_reg p_instr[25:22]
  parameter R0    = 4'b0000, R1    = 4'b0001, R2    = 4'b0010, R3    = 4'b0011,
            R4    = 4'b0100, R5    = 4'b0101, R6    = 4'b0110, R7    = 4'b0111,
            R8    = 4'b1000, R9    = 4'b1001, DIS   = 4'b1010, ROUT  = 4'b1011,
            NORTH = 4'b1100, SOUTH = 4'b1101, EAST  = 4'b1110, WEST  = 4'b1111;
`define    outres p_instr[21:14]
`define    regres p_instr[13:6]
`define     carry p_instr[5:4]
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN1
  //  and IN2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  parameter C_DIS = 2'b00,  //  do not compute carry (do an ALU operation)
            C_CAR = 2'b01,  //  compute carry using carry flag for carry-in
            C_ZER = 2'b10,  //  compute carry using 0 for carry-in
            C_ONE = 2'b11;  //  compute carry using 1 for carry-in
`define   alu_dis p_instr[3]  //  allow disabling of ALU operation, 1=allow
`define alu_dis_s p_instr[2]  //  sense of PE disable bit for ALU op, 1=invert
`define   mem_dis p_instr[1]  //  allow disabling of memory operation....
`define mem_dis_s p_instr[0]  //  sense of PE disable bit for memory op....

//  PE flag definitions and bit positions:
//    Note that flags other than carry are not affected by a carry operation,
//    and the carry flag is not affected by an ALU operation.
`define reg_msb_f p_flags[9]   //  m.s.b. of destination register
`define reg_zer_f p_flags[8]   //  if destination register = 0
`define out_msb_f p_flags[7]   //  m.s.b. of register OUT
`define out_zer_f p_flags[6]   //  if register OUT = 0
`define in2_msb_f p_flags[5]   //  m.s.b. of register IN2
`define in2_zer_f p_flags[4]   //  if register IN2 = 0
`define in1_msb_f p_flags[3]   //  m.s.b. of register IN1
`define in1_zer_f p_flags[2]   //  if register IN1 = 0
`define disable_f p_flags[1]   //  state of PE disable bit
`define   carry_f p_flags[0]   //  result of last carry operation

assign n_out = regs[NORTH],
       s_out = regs[SOUTH],
       east  = regs[EAST],  //  cannot access structure of regs[i]!!!
       e_out = east[WORD_WIDTH-1],
       west  = regs[WEST],  //  cannot access structure of regs[i]!!!
       w_out = west[0],
       r_out = regs[ROUT];

initial
  begin
    reg_dump_ct = 0;
    mem_dump_ct = 0;
    clock_ct    = 0;
  end


always @ (posedge p_clock)
  begin // instruction cycle

    clock_ct = clock_ct + 1;
    last_out = out;             //  save OUT reg for mem op
    temp_dis = regs[DIS] || 0;  //  save disable reg for mem op

    //  if ALU/carry operations not disabled, then perform one
    if ( ~(`alu_dis & (`alu_dis_s ^ temp_dis)) )
      begin

        //  carry setup or register read
        case (`carry)
          C_DIS:
            begin
              case (`srce_reg)
                ROUT:  temp = r_in2;
                  //  should be temp = r_in (default) (port from router), but
                  //  router doesn't exist, but router supposed to produce
                  //  carry word, so PE will produce carry word and place in 
                  //  register r_in2, thus r_in doesn't really work
                EAST:
                  begin
                    temp = regs[EAST] << 1;
                    temp[0] = e_in;
                  end
                WEST:
                  begin
                    temp = regs[WEST] >> 1;
                    temp[WORD_WIDTH-1] = w_in;
                  end
                default temp = regs[`srce_reg];
              endcase
              out_res = `outres;  //  cannot access structure of `outres!!!
              reg_res = `regres;  //  cannot access structure of `regres!!!
            end
          C_CAR: temp = `carry_f;
          C_ZER: temp = 0;
          C_ONE: temp = 1;
        endcase

        //  carry or ALU computation
        if (`carry)
          for (i=0; i<WORD_WIDTH; i=i+1)
            temp[i+1] = in_1[i]&in_2[i] | in_1[i]&temp[i] | in_2[i]&temp[i];
        else
          for (i=0; i<WORD_WIDTH; i=i+1)
            begin
              out[i]  = out_res[{in_1[i],in_2[i],temp[i]}];
              temp[i] = reg_res[{in_1[i],in_2[i],temp[i]}];
            end

        //  register writeback and flag setup
        if (`carry)
          begin
            r_in2 = temp;
            `carry_f = temp[WORD_WIDTH];
          end
        else
          begin
            regs[`dest_reg] = temp;
            `disable_f = regs[DIS] || 0;
            `out_zer_f = ~out;
            `out_msb_f = out[WORD_WIDTH-1];
            `reg_zer_f = ~temp[WORD_WIDTH-1:0];
            `reg_msb_f = temp[WORD_WIDTH-1];
          end

      end // of carry or ALU operation

    //  if memory operations not disabled, then perform one
    if ( ~(`mem_dis & (`mem_dis_s ^ temp_dis)) )
      case (`mem_ctrl)
        NO_OP: ;
        R_OUT: mem[`mem_addr] = last_out;
        W_IN1:
          begin
            in_1 = mem[`mem_addr];
            `in1_zer_f = ~in_1;
            `in1_msb_f = in_1[WORD_WIDTH-1];
          end
        W_IN2:
          begin
            in_2 = mem[`mem_addr];
            `in2_zer_f = ~in_2;
            `in2_msb_f = in_2[WORD_WIDTH-1];
          end
      endcase

  end // of instruction cycle


always @ (posedge p_reset)
  begin
    for (i=0; i<16; i=i+1) regs[i] = 0;
    p_flags     = 0;
    in_1        = 0;
    in_2        = 0;
    out         = 0;
    m_out       = 0;
    r_in2       = 0;
  end


always @ (posedge m_clock)
  if (m_write) mem[m_addr] = m_in;
  else m_out = mem[m_addr];


always @ (posedge dump_reg)
  begin
    $display("PE \"%s\" Binary Port and Register Dump # %0d, Clock Cycle # %0d",
             PE_NAME, reg_dump_ct, clock_ct);
    reg_dump_ct = reg_dump_ct + 1;
    $display("  PE_INSTR: mem_addr");
    $display("            %b", `mem_addr);
    $display("            mem_ctrl  dest_reg  srce_reg  out_res   reg_res");
    $display("               %b       %b      %b    %b  %b",
              `mem_ctrl, `dest_reg, `srce_reg, `outres, `regres);
    $display("            carry  alu_dis  alu_dis_s  mem_dis  mem_dis_s  (p)");
    $display("              %b      %b         %b         %b         %b",
              `carry, `alu_dis, `alu_dis_s, `mem_dis, `mem_dis_s);
    $write  ("     FLAGS: reg<0  reg=0  out<0  out=0  in2<0");
      $display("  in2=0  in1<0  in1=0");
    $write  ("              %b      %b      %b      %b      %b",
              `reg_msb_f, `reg_zer_f, `out_msb_f, `out_zer_f, `in2_msb_f);
      $display("      %b      %b      %b", `in2_zer_f, `in1_msb_f, `in1_zer_f);
    $display("            disab  carry  (r)");
    $display("              %b      %b", `disable_f, `carry_f);
    $display("       IN1: %b (r)", in_1);
    $display("       IN2: %b (r)", in_2);
    $display("       OUT: %b (r)", out);
    $display("        R0: %b (r)", regs[R0]);
    $display("        R1: %b (r)", regs[R1]);
    $display("        R2: %b (r)", regs[R2]);
    $display("        R3: %b (r)", regs[R3]);
    $display("        R4: %b (r)", regs[R4]);
    $display("        R5: %b (r)", regs[R5]);
    $display("        R6: %b (r)", regs[R6]);
    $display("        R7: %b (r)", regs[R7]);
    $display("        R8: %b (r)", regs[R8]);
    $display("        R9: %b (r)", regs[R9]);
    $display("       DIS: %b (r)", regs[DIS]);
    $display("     R_OUT: %b (r)", regs[ROUT]);
    $display("      R_IN: %b (p/r)", r_in2);  //  see note in register read
    $display("     N_OUT: %b (r)", regs[NORTH]);
    $display("      N_IN: %b (p)", n_in);
    $display("     S_OUT: %b (r)", regs[SOUTH]);
    $display("      S_IN: %b (p)", s_in);
    $display("      EAST: %b (r)   E_IN: %b (p)", regs[EAST], e_in);
    $display("      W_IN: %b (p)   WEST: %b (r)", w_in, regs[WEST]);
  end


always @ (posedge dump_mem)
  begin
    $display("PE \"%s\" Hexidecimal Memory Dump # %0d, Clock Clycle # %0d", 
             PE_NAME, mem_dump_ct, clock_ct);
    mem_dump_ct = mem_dump_ct + 1;
    i = 32/(WORD_WIDTH/4);
    if (i == 0) i = 1; 
    for (r=0; r<MEM_LENGTH; r=r+i)
      begin
        $write("  %h: ",r);
        for (j=0; j<i; j=j+1) $write(" %h",mem[r+j]);
        $display;
      end
  end


endmodule // pe0



//\\//\\//\\//\\//\\//\\//\\//\\//\\

//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\



module pe // adds multiple-destination memory bus to pe0
  (p_clock, p_reset, p_instr, p_flags,
   n_in, s_in, e_in, w_in, r_in, 
   n_out, s_out, e_out, w_out, r_out,
   m_clock, m_write, m_addr, m_in, m_out,
   dump_reg, dump_mem);

parameter // defaults, should be overridden by instantiating module:
  ADDR_WIDTH  = 10,           //  width of PE memory address, in bits
  WORD_WIDTH  = 32,           //  width of PE data word, in bits
  MEM_LENGTH  = 1024,         //  length of PE memory, in words
  PE_NAME     = "undefined";  //  name of PE for dump identification

input // (1 bit wide)
  p_clock, p_reset,     //  PE clock & reset, rising-edge triggered
  e_in, w_in,           //  east (lsb) & west (msb) communication
  m_clock,              //  PE memory clock for external access, rising-edge
  m_write,              //  PE memory read/write control for external access:
                        //    read = 0, write = 1
  dump_reg, dump_mem;   //  PE register & memory dump clocks, rising-edge
input  [ADDR_WIDTH-1:0] 
  m_addr;               //  PE memory address for external access
input  [WORD_WIDTH-1:0]
  n_in, s_in, r_in,     //  PE north & south & router (word) communication
  m_in;                 //  PE memory data for external access
input  [ADDR_WIDTH+34-1:0] 
  p_instr;              //  PE microinstruction (described below)
output // (1 bit wide)
  e_out, w_out;         //  east (msb) & west (lsb) communication
output [9:0] 
  p_flags;              //  PE condition flags (described below)
output [WORD_WIDTH-1:0] 
  n_out, s_out, r_out,  //  PE north & south & router (word) communication
  m_out;                //  PE memory data for external access

reg temp_dis; // (1 bit wide)
reg [7:0] reg_res, out_res;
reg [9:0] p_flags;
reg [ADDR_WIDTH-1:0] r;
reg [WORD_WIDTH-1:0] mem[0:MEM_LENGTH-1],
                     regs[0:15],
                     in_1, in_2, out, m_out,
                     last_out, r_in2;
reg [WORD_WIDTH:0] temp;
wire e_out, w_out;
wire [WORD_WIDTH-1:0] re, rw;
integer i, j, k, reg_dump_ct, mem_dump_ct, clock_ct;

//  PE microinstruction field definitions and content parameters:
`define   mb_addr p_instr[ADDR_WIDTH+34-1:34]  //  memory bus transfer address
`define   mb_srce p_instr[33]  //  mem bus transfer source is mem (1) or out (0)
`define  mb_d_mem p_instr[32]  //  memory bus transfer dest is memory, 1=true
`define  mb_d_in2 p_instr[31]  //  memory bus transfer dest is IN2, 1=true
`define  mb_d_in1 p_instr[30]  //  memory bus transfer dest is IN1, 1=true
`define  srce_reg p_instr[29:26]  //  source register of ALU operation...
`define    regres p_instr[25:18]  //  ALU operand for dest register result
`define  dest_reg p_instr[17:14]  //  destination register of ALU operation...
`define    outres p_instr[13:6]   //  ALU operand for OUT register result
  //  mnemonics for srce_reg and dest_reg values:
  parameter R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
            R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
            R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
            RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111;
`define     carry p_instr[5:4]
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN1
  //  and IN2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.  Mnemonics for carry:
  parameter CN = 2'b00,  //  do not compute carry (do an ALU operation)
            CC = 2'b01,  //  compute carry using carry flag for carry-in
            C0 = 2'b10,  //  compute carry using 0 for carry-in
            C1 = 2'b11;  //  compute carry using 1 for carry-in
`define   alu_dis p_instr[3]  //  allow disabling of ALU operation, 1=allow
`define alu_dis_i p_instr[2]  //  invert PE disable bit for ALU op, 1=invert
`define    mb_dis p_instr[1]  //  allow disabling of memory bus operation....
`define  mb_dis_i p_instr[0]  //  invert PE disable bit for memory bus op....

//  PE condition flag definitions and condition code register bit positions:
//    Note that flags other than carry are not affected by a carry operation,
//    and the carry flag is not affected by an ALU operation.
`define reg_msb_f p_flags[9]   //  m.s.b. of destination register
`define reg_zer_f p_flags[8]   //  if destination register == 0
`define out_msb_f p_flags[7]   //  m.s.b. of register OUT
`define out_zer_f p_flags[6]   //  if register OUT == 0
`define in2_msb_f p_flags[5]   //  m.s.b. of register IN2
`define in2_zer_f p_flags[4]   //  if register IN2 == 0
`define in1_msb_f p_flags[3]   //  m.s.b. of register IN1
`define in1_zer_f p_flags[2]   //  if register IN1 == 0
`define disable_f p_flags[1]   //  state of PE disable bit
`define   carry_f p_flags[0]   //  carry-out of last carry operation

assign n_out = regs[RN],
       s_out = regs[RS],
       re    = regs[RE],  //  since cannot access bits of regs[i]!!!
       e_out = re[WORD_WIDTH-1],
       rw    = regs[RW],  //  since cannot access bits of regs[i]!!!
       w_out = rw[0],
       r_out = regs[RR];


initial
  begin
    reg_dump_ct = 0;
    mem_dump_ct = 0;
    clock_ct    = 0;
  end


//  reset
always @ (posedge p_reset)
  begin
    for (i=0; i<16; i=i+1) regs[i] = 0;
    p_flags     = 0;
    in_1        = 0;
    in_2        = 0;
    out         = 0;
    m_out       = 0;
    r_in2       = 0;
    $display("PE \"%s\" Reset, Clock Cycle # %0d", PE_NAME, clock_ct);
  end


//  instruction cycle
always @ (posedge p_clock)
  begin

    last_out = out;            //  save OUT reg for mem op
    temp_dis = regs[RD] || 0;  //  save disable reg for mem op

    //  ALU or carry operation
    if ( ~(`alu_dis & (`alu_dis_i ^ temp_dis)) )  //  ALU/carry ops not disabled
      begin

        //  register read
        case (`carry)
          CN:
            begin
              case (`srce_reg)
                RN: temp = n_in;
                RS: temp = s_in;
                RE:
                  begin
                    temp = regs[RE] << 1;
                    temp[0] = e_in;
                  end
                RW:
                  begin
                    temp = regs[RW] >> 1;
                    temp[WORD_WIDTH-1] = w_in;
                  end
                RR:  temp = r_in2;
                  //  should be temp = r_in (port from router), but router
                  //  doesn't exist, but router supposed to produce carry
                  //  word, so PE will produce carry word and place in 
                  //  register r_in2, thus r_in doesn't really work
                default temp = regs[`srce_reg];
              endcase
              out_res = `outres;  //  cannot access structure of `outres!!!
              reg_res = `regres;  //  cannot access structure of `regres!!!
            end
          CC: temp = `carry_f;
          C0: temp = 0;
          C1: temp = 1;
        endcase

        //  operation execution
        if (`carry)  //  carry operation
          for (i=0; i<WORD_WIDTH; i=i+1)
            temp[i+1] = in_1[i]&in_2[i] | in_1[i]&temp[i] | in_2[i]&temp[i];
        else  //  ALU operation 
          for (i=0; i<WORD_WIDTH; i=i+1)
            begin
              out[i]  = out_res[{in_1[i],in_2[i],temp[i]}];
              temp[i] = reg_res[{in_1[i],in_2[i],temp[i]}];
            end

        //  register writeback and flag setup
        if (`carry)  //  carry operation
          begin
            r_in2 = temp;  //  see note in register read
            `carry_f = temp[WORD_WIDTH];
          end
        else  //  ALU operation
          begin
            regs[`dest_reg] = temp;
            `disable_f = regs[RD] || 0;
            `out_zer_f = !out;
            `out_msb_f = out[WORD_WIDTH-1];
            `reg_zer_f = !temp[WORD_WIDTH-1:0];
            `reg_msb_f = temp[WORD_WIDTH-1];
          end

      end  //  of carry or ALU operation

    //  memory operation
    if ( ~(`mb_dis & (`mb_dis_i ^ temp_dis)) )    //  memory ops not disabled
      begin
        if (`mb_srce) temp = mem[`mb_addr];       //  `mb_srce == memory
        else
          begin
            temp = last_out;                      //  `mb_srce == OUT register
            if (`mb_d_mem) mem[`mb_addr] = temp;  //  disallow mem to mem op
          end
        if (`mb_d_in2)
            begin
              in_2 = temp;
              `in2_zer_f = !in_2;
              `in2_msb_f = in_2[WORD_WIDTH-1];
            end
        if (`mb_d_in1)
            begin
              in_1 = temp;
              `in1_zer_f = !in_1;
              `in1_msb_f = in_1[WORD_WIDTH-1];
            end
      end

    clock_ct = clock_ct + 1;

  end  // of instruction cycle


//  memory access
always @ (posedge m_clock)
  if (m_write) mem[m_addr] = m_in;
  else m_out = mem[m_addr];


//  register dump
always @ (posedge dump_reg)
  begin
    $display("PE \"%s\" Port and Register Dump # %0d, Clock Cycle # %0d",
             PE_NAME, reg_dump_ct, clock_ct);
    reg_dump_ct = reg_dump_ct + 1;
    $display("  PE_INSTR: mb_addr");
    $display("            %b", `mb_addr);
    $write  ("            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  srce_reg");
      $display("  reg_res  dest_reg");
    $write  ("               %b        %b         %b         %b        %b",
              `mb_srce, `mb_d_mem, `mb_d_in2, `mb_d_in1, `srce_reg);
      $display("    %b   %b", `regres, `dest_reg);
    $write  ("            out_res  carry  alu_dis  alu_dis_i  mb_dis");
      $display("  mb_dis_i  (p)");
    $display("            %b   %b      %b         %b        %b        %b",
              `outres, `carry, `alu_dis, `alu_dis_i, `mb_dis, `mb_dis_i);
    $write  ("     FLAGS: reg<0  reg=0  out<0  out=0  in2<0");
      $display("  in2=0  in1<0  in1=0");
    $write  ("              %b      %b      %b      %b      %b",
              `reg_msb_f, `reg_zer_f, `out_msb_f, `out_zer_f, `in2_msb_f);
      $display("      %b      %b      %b", `in2_zer_f, `in1_msb_f, `in1_zer_f);
    $display("            disab  carry  (r)");
    $display("              %b      %b", `disable_f, `carry_f);
    $display("       IN1: %b (r)", in_1);
    $display("       IN2: %b (r)", in_2);
    $display("       OUT: %b (r)", out);
    $display("        R0: %b (r)", regs[R0]);
    $display("        R1: %b (r)", regs[R1]);
    $display("        R2: %b (r)", regs[R2]);
    $display("        R3: %b (r)", regs[R3]);
    $display("        R4: %b (r)", regs[R4]);
    $display("        R5: %b (r)", regs[R5]);
    $display("        R6: %b (r)", regs[R6]);
    $display("        R7: %b (r)", regs[R7]);
    $display("        R8: %b (r)", regs[R8]);
    $display("        R9: %b (r)", regs[R9]);
    $display("   DISABLE: %b (r)", regs[RD]);
    $display("    ROUTER: %b (r)", regs[RR]);
    $display("      R_IN: %b (p/r)", r_in2);  //  see note in register read
    $display("     NORTH: %b (r)", regs[RN]);
    $display("      N_IN: %b (p)", n_in);
    $display("     SOUTH: %b (r)", regs[RS]);
    $display("      S_IN: %b (p)", s_in);
    $display("      EAST: %b (r)   E_IN: %b (p)", regs[RE], e_in);
    $display("      W_IN: %b (p)   WEST: %b (r)", w_in, regs[RW]);
  end


//  memory dump
always @ (posedge dump_mem)
  begin
    $display("PE \"%s\" Memory Dump # %0d, Clock Clycle # %0d", 
             PE_NAME, mem_dump_ct, clock_ct);
    mem_dump_ct = mem_dump_ct + 1;
    i = 32/(WORD_WIDTH/4);
    if (i == 0) i = 1;
    r = 0;
    for (k=0; k<MEM_LENGTH; k=k+i)
      begin
        $write("  %h: ",r);
        for (j=0; j<i; j=j+1) $write(" %h",mem[r+j]);
        $display;
        r = r + i;
      end
  end


endmodule // pe



//\\//\\//\\//\\//\\//\\//\\//\\//\\

//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\



module pe2 // adds variable-shift east & west registers to pe
  (p_clock, p_reset, p_instr, p_flags,
   n_in, s_in, e_in, w_in, r_in, 
   n_out, s_out, e_out, w_out, r_out,
   m_clock, m_write, m_addr, m_in, m_out,
   dump_reg, dump_mem);

parameter // defaults, should be overridden by instantiating module:
  ADDR_WIDTH  = 10,           //  width of PE memory address, in bits
  WORD_WIDTH  = 32,           //  width of PE data word, in bits
  MEM_LENGTH  = 1024,         //  length of PE memory, in words
  PE_NAME     = "undefined";  //  name of PE for dump identification

input // (1 bit wide)
  p_clock, p_reset,     //  PE clock & reset, rising-edge triggered
  e_in, w_in,           //  east (lsb) & west (msb) communication
  m_clock,              //  PE memory clock for external access, rising-edge
  m_write,              //  PE memory read/write control for external access:
                        //    read = 0, write = 1
  dump_reg, dump_mem;   //  PE register & memory dump clocks, rising-edge
input  [ADDR_WIDTH-1:0] 
  m_addr;               //  PE memory address for external access
input  [WORD_WIDTH-1:0]
  n_in, s_in, r_in,     //  PE north & south & router (word) communication
  m_in;                 //  PE memory data for external access
input  [ADDR_WIDTH+40-1:0] 
  p_instr;              //  PE microinstruction (described below)
output // (1 bit wide)
  e_out, w_out;         //  east (msb) & west (lsb) communication
output [9:0] 
  p_flags;              //  PE condition flags (described below)
output [WORD_WIDTH-1:0] 
  n_out, s_out, r_out,  //  PE north & south & router (word) communication
  m_out;                //  PE memory data for external access

reg temp_dis; // (1 bit wide_
reg [7:0] reg_res, out_res;
reg [9:0] p_flags;
reg [ADDR_WIDTH-1:0] r;
reg [WORD_WIDTH-1:0] mem[0:MEM_LENGTH-1],
                     regs[0:15],
                     in_1, in_2, out, m_out,
                     last_out, r_in2;
reg [WORD_WIDTH:0] temp;
wire e_out, w_out;
wire [WORD_WIDTH-1:0] re, rw;
integer i, j, k, reg_dump_ct, mem_dump_ct, clock_ct;

//  PE microinstruction field definitions and content parameters:
`define   mb_addr p_instr[ADDR_WIDTH+40-1:40]  //  memory bus transfer address
`define   mb_srce p_instr[39]  //  mem bus transfer source is mem (1) or out (0)
`define  mb_d_mem p_instr[38]  //  memory bus transfer dest is memory, 1=true
`define  mb_d_in2 p_instr[37]  //  memory bus transfer dest is IN2, 1=true
`define  mb_d_in1 p_instr[36]  //  memory bus transfer dest is IN1, 1=true
`define  srce_reg p_instr[35:32]  //  source register of ALU operation...
`define     shift p_instr[31:26]  //  shift east or west source reg "shift" bits
`define    regres p_instr[25:18]  //  ALU operand for dest register result
`define  dest_reg p_instr[17:14]  //  destination register of ALU operation...
`define    outres p_instr[13:6]   //  ALU operand for OUT register result
  //  mnemonics for srce_reg and dest_reg values:
  parameter R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
            R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
            R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
            RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111;
`define     carry p_instr[5:4]
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN1
  //  and IN2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.  Mnemonics for carry:
  parameter CN = 2'b00,  //  do not compute carry (do an ALU operation)
            CC = 2'b01,  //  compute carry using carry flag for carry-in
            C0 = 2'b10,  //  compute carry using 0 for carry-in
            C1 = 2'b11;  //  compute carry using 1 for carry-in
`define   alu_dis p_instr[3]  //  allow disabling of ALU operation, 1=allow
`define alu_dis_i p_instr[2]  //  invert PE disable bit for ALU op, 1=invert
`define    mb_dis p_instr[1]  //  allow disabling of memory bus operation....
`define  mb_dis_i p_instr[0]  //  invert PE disable bit for memory bus op....

//  PE condition flag definitions and condition code register bit positions:
//    Note that flags other than carry are not affected by a carry operation,
//    and the carry flag is not affected by an ALU operation.
`define reg_msb_f p_flags[9]   //  m.s.b. of destination register
`define reg_zer_f p_flags[8]   //  if destination register == 0
`define out_msb_f p_flags[7]   //  m.s.b. of register OUT
`define out_zer_f p_flags[6]   //  if register OUT == 0
`define in2_msb_f p_flags[5]   //  m.s.b. of register IN2
`define in2_zer_f p_flags[4]   //  if register IN2 == 0
`define in1_msb_f p_flags[3]   //  m.s.b. of register IN1
`define in1_zer_f p_flags[2]   //  if register IN1 == 0
`define disable_f p_flags[1]   //  state of PE disable bit
`define   carry_f p_flags[0]   //  carry-out of last carry operation

assign n_out = regs[RN],
       s_out = regs[RS],
       re    = regs[RE],  //  since cannot access bits of regs[i]!!!
       e_out = re[WORD_WIDTH-1],
       rw    = regs[RW],  //  since cannot access bits of regs[i]!!!
       w_out = rw[0],
       r_out = regs[RR];


initial
  begin
    reg_dump_ct = 0;
    mem_dump_ct = 0;
    clock_ct    = 0;
  end


//  reset
always @ (posedge p_reset)
  begin
    for (i=0; i<16; i=i+1) regs[i] = 0;
    p_flags     = 0;
    in_1        = 0;
    in_2        = 0;
    out         = 0;
    m_out       = 0;
    r_in2       = 0;
    $display("PE \"%s\" Reset, Clock Cycle # %0d", PE_NAME, clock_ct);
  end


//  instruction cycle
always @ (posedge p_clock)
  begin

    last_out = out;            //  save OUT reg for mem op
    temp_dis = regs[RD] || 0;  //  save disable reg for mem op

    //  ALU or carry operation
    if ( ~(`alu_dis & (`alu_dis_i ^ temp_dis)) )  //  ALU/carry ops not disabled
      begin

        //  register read
        case (`carry)
          CN:
            begin
              case (`srce_reg)
                RN: temp = n_in;
                RS: temp = s_in;
                RE:
                  begin
                    temp = regs[RE] << `shift % WORD_WIDTH;
                    if (e_in) for (i=0; i<`shift%WORD_WIDTH; i=i+1) temp[i] = 1;
                    //  since Verilog doesn't allow variable part-select!!!
                  end
                RW:
                  begin
                    temp = regs[RW] >> `shift % WORD_WIDTH;
                    if (w_in) for (i=0; i<`shift%WORD_WIDTH; i=i+1)
                                  temp[WORD_WIDTH-1-i] = 1;
                    //  since Verilog doesn't allow variable part-select!!!
                  end
                RR:  temp = r_in2;
                  //  should be temp = r_in (port from router), but router
                  //  doesn't exist, but router supposed to produce carry
                  //  word, so PE will produce carry word and place in 
                  //  register r_in2, thus r_in doesn't really work
                default temp = regs[`srce_reg];
              endcase
              out_res = `outres;  //  since cannot access bits of `outres!!!
              reg_res = `regres;  //  since cannot access bits of `regres!!!
            end
          CC: temp = `carry_f;
          C0: temp = 0;
          C1: temp = 1;
        endcase

        //  operation execution
        if (`carry)  //  carry operation
          for (i=0; i<WORD_WIDTH; i=i+1)
            temp[i+1] = in_1[i]&in_2[i] | in_1[i]&temp[i] | in_2[i]&temp[i];
        else  //  ALU operation
          for (i=0; i<WORD_WIDTH; i=i+1)
            begin
              out[i]  = out_res[{in_1[i],in_2[i],temp[i]}];
              temp[i] = reg_res[{in_1[i],in_2[i],temp[i]}];
            end

        //  register writeback and flag setup
        if (`carry)  //  carry operation
          begin
            r_in2 = temp;  //  see note in register read
            `carry_f = temp[WORD_WIDTH];
          end
        else  //  ALU operation
          begin
            regs[`dest_reg] = temp;
            `disable_f = regs[RD] || 0;
            `out_zer_f = !out;
            `out_msb_f = out[WORD_WIDTH-1];
            `reg_zer_f = !temp[WORD_WIDTH-1:0];
            `reg_msb_f = temp[WORD_WIDTH-1];
          end

      end  //  of ALU or cary operation

    //  memory operation
    if ( ~(`mb_dis & (`mb_dis_i ^ temp_dis)) )    //  memory ops not disabled
      begin
        if (`mb_srce) temp = mem[`mb_addr];       //  `mb_srce == memory
        else
          begin
            temp = last_out;                      //  `mb_srce == OUT register
            if (`mb_d_mem) mem[`mb_addr] = temp;  //  disallow mem to mem op
          end
        if (`mb_d_in2)
            begin
              in_2 = temp;
              `in2_zer_f = !in_2;
              `in2_msb_f = in_2[WORD_WIDTH-1];
            end
        if (`mb_d_in1)
            begin
              in_1 = temp;
              `in1_zer_f = !in_1;
              `in1_msb_f = in_1[WORD_WIDTH-1];
            end
      end

    clock_ct = clock_ct + 1;

  end  //  of instruction cycle


//  memory access
always @ (posedge m_clock)
  if (m_write) mem[m_addr] = m_in;
  else m_out = mem[m_addr];


//  register dump
always @ (posedge dump_reg)
  begin
    $display("PE \"%s\" Port and Register Dump # %0d, Clock Cycle # %0d",
             PE_NAME, reg_dump_ct, clock_ct);
    reg_dump_ct = reg_dump_ct + 1;
    $display("  PE_INSTR: mb_addr");
    $display("            %b", `mb_addr);
    $write  ("            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  srce_reg");
      $display("  shift  reg_res");
    $write  ("               %b        %b         %b         %b        %b",
              `mb_srce, `mb_d_mem, `mb_d_in2, `mb_d_in1, `srce_reg);
      $display("   %b  %b", `shift, `regres);
    $write  ("            dest_reg  out_res  carry  alu_dis  alu_dis_i");
      $display("  mb_dis  mb_dis_i  (p)");
    $write  ("              %b    %b  %b       %b         %b        %b",
              `dest_reg, `outres, `carry, `alu_dis, `alu_dis_i, `mb_dis);
      $display("        %b", `mb_dis_i);
    $write  ("     FLAGS: reg<0  reg=0  out<0  out=0  in2<0");
      $display("  in2=0  in1<0  in1=0");
    $write  ("              %b      %b      %b      %b      %b",
              `reg_msb_f, `reg_zer_f, `out_msb_f, `out_zer_f, `in2_msb_f);
      $display("      %b      %b      %b", `in2_zer_f, `in1_msb_f, `in1_zer_f);
    $display("            disab  carry  (r)");
    $display("              %b      %b", `disable_f, `carry_f);
    $display("       IN1: %b (r)", in_1);
    $display("       IN2: %b (r)", in_2);
    $display("       OUT: %b (r)", out);
    $display("        R0: %b (r)", regs[R0]);
    $display("        R1: %b (r)", regs[R1]);
    $display("        R2: %b (r)", regs[R2]);
    $display("        R3: %b (r)", regs[R3]);
    $display("        R4: %b (r)", regs[R4]);
    $display("        R5: %b (r)", regs[R5]);
    $display("        R6: %b (r)", regs[R6]);
    $display("        R7: %b (r)", regs[R7]);
    $display("        R8: %b (r)", regs[R8]);
    $display("        R9: %b (r)", regs[R9]);
    $display("   DISABLE: %b (r)", regs[RD]);
    $display("    ROUTER: %b (r)", regs[RR]);
    $display("      R_IN: %b (p/r)", r_in2);  //  see note in register read
    $display("     NORTH: %b (r)", regs[RN]);
    $display("      N_IN: %b (p)", n_in);
    $display("     SOUTH: %b (r)", regs[RS]);
    $display("      S_IN: %b (p)", s_in);
    $display("      EAST: %b (r)   E_IN: %b (p)", regs[RE], e_in);
    $display("      W_IN: %b (p)   WEST: %b (r)", w_in, regs[RW]);
  end


//  memory dump
always @ (posedge dump_mem)
  begin
    $display("PE \"%s\" Memory Dump # %0d, Clock Clycle # %0d", 
             PE_NAME, mem_dump_ct, clock_ct);
    mem_dump_ct = mem_dump_ct + 1;
    i = 32/(WORD_WIDTH/4);
    if (i == 0) i = 1;
    r = 0;
    for (k=0; k<MEM_LENGTH; k=k+i)
      begin
        $write("  %h: ",r);
        for (j=0; j<i; j=j+1) $write(" %h",mem[r+j]);
        $display;
        r = r + i;
      end
  end


endmodule // pe2



//\\//\\//\\//\\//\\//\\//\\//\\//\\

//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\



module pe3 // adds complementation to carry computation of pe2
  (p_clock, p_reset, p_instr, p_flags,
   n_in, s_in, e_in, w_in, r_in, 
   n_out, s_out, e_out, w_out, r_out,
   m_clock, m_write, m_addr, m_in, m_out,
   dump_reg, dump_mem);

parameter // defaults, should be overridden by instantiating module:
  ADDR_WIDTH  = 10,           //  width of PE memory address, in bits
  WORD_WIDTH  = 32,           //  width of PE data word, in bits
  MEM_LENGTH  = 1024,         //  length of PE memory, in words
  PE_NAME     = "undefined";  //  name of PE for dump identification

input // (1 bit wide)
  p_clock, p_reset,     //  PE clock & reset, rising-edge triggered
  e_in, w_in,           //  east (lsb) & west (msb) communication
  m_clock,              //  PE memory clock for external access, rising-edge
  m_write,              //  PE memory read/write control for external access:
                        //    read = 0, write = 1
  dump_reg, dump_mem;   //  PE register & memory dump clocks, rising-edge
input  [ADDR_WIDTH-1:0] 
  m_addr;               //  PE memory address for external access
input  [WORD_WIDTH-1:0]
  n_in, s_in, r_in,     //  PE north & south & router (word) communication
  m_in;                 //  PE memory data for external access
input  [ADDR_WIDTH+44-1:0] 
  p_instr;              //  PE microinstruction (described below)
output // (1 bit wide)
  e_out, w_out;         //  east (msb) & west (lsb) communication
output [9:0] 
  p_flags;              //  PE condition flags (described below)
output [WORD_WIDTH-1:0] 
  n_out, s_out, r_out,  //  PE north & south & router (word) communication
  m_out;                //  PE memory data for external access

reg temp_dis; // (1 bit wide)
reg [7:0] reg_res, out_res;
reg [9:0] p_flags;
reg [ADDR_WIDTH-1:0] r;
reg [WORD_WIDTH-1:0] mem[0:MEM_LENGTH-1],
                     regs[0:15],
                     in_1, in_2, out, m_out,
                     last_out;
reg [WORD_WIDTH:0] temp;
wire e_out, w_out;
wire [WORD_WIDTH-1:0] re, rw;
integer i, j, k, reg_dump_ct, mem_dump_ct, clock_ct;

//  PE microinstruction field definitions and content parameters:
`define   mb_addr p_instr[ADDR_WIDTH+44-1:44]  //  memory bus transfer address
`define   mb_srce p_instr[43]  //  mem bus transfer source is mem (1) or out (0)
`define  mb_d_mem p_instr[42]  //  memory bus transfer dest is memory, 1=true
`define  mb_d_in2 p_instr[41]  //  memory bus transfer dest is IN2, 1=true
`define  mb_d_in1 p_instr[40]  //  memory bus transfer dest is IN1, 1=true
`define  srce_reg p_instr[39:36]  //  source register of ALU operation...
`define     shift p_instr[35:30]  //  shift east or west source reg "shift" bits
`define    regres p_instr[29:22]  //  ALU operand for dest register result
`define  dest_reg p_instr[21:18]  //  destination register of ALU operation...
`define    outres p_instr[17:10]  //  ALU operand for OUT register result
  //  mnemonics for srce_reg and dest_reg values:
  parameter R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
            R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
            R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
            RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111;
  //  Note:  The PE only does EITHER an ALU OR a carry operation in one
  //  instruction cycle.  A carry word is computed using registers IN1 and/or
  //  IN/2 and a carry-in bit, and a carry operation is implied by specifying
  //  the registers to use.  The carry word is made available at the input
  //  from the router, r_in, and the carry-out is placed in the carry flag of
  //  the p_flags register.
`define   car_in1 p_instr[9]  //  use IN1 in carry word computation, 1=true
`define   car_in2 p_instr[8]  //  use IN2 in carry word computation, 1=true
`define  car_nin1 p_instr[7]  //  use inverse of IN1 (if used), 1=true
`define  car_nin2 p_instr[6]  //  use inverse of IN2 (if used), 1=true
`define  car_srce p_instr[5]  //  use value for carry-in (or carry flag) 1=true
`define   car_val p_instr[4]  //  use 1 for c-in value (or 0; if used), 1=true
`define   alu_dis p_instr[3]  //  allow disabling of ALU operation, 1=allow
`define alu_dis_i p_instr[2]  //  invert PE disable bit for ALU op, 1=invert
`define    mb_dis p_instr[1]  //  allow disabling of memory bus operation....
`define  mb_dis_i p_instr[0]  //  invert PE disable bit for memory bus op....

//  PE condition flag definitions and condition code register bit positions:
//    Note that flags other than carry are not affected by a carry operation,
//    and the carry flag is not affected by an ALU operation.
`define reg_msb_f p_flags[9]   //  m.s.b. of destination register
`define reg_zer_f p_flags[8]   //  if destination register == 0
`define out_msb_f p_flags[7]   //  m.s.b. of register OUT
`define out_zer_f p_flags[6]   //  if register OUT == 0
`define in2_msb_f p_flags[5]   //  m.s.b. of register IN2
`define in2_zer_f p_flags[4]   //  if register IN2 == 0
`define in1_msb_f p_flags[3]   //  m.s.b. of register IN1
`define in1_zer_f p_flags[2]   //  if register IN1 == 0
`define disable_f p_flags[1]   //  state of PE disable bit
`define   carry_f p_flags[0]   //  carry-out of last carry operation

assign n_out = regs[RN],
       s_out = regs[RS],
       re    = regs[RE],  //  since cannot access bits of regs[i]!!!
       e_out = re[WORD_WIDTH-1],
       rw    = regs[RW],  //  since cannot access bits of regs[i]!!!
       w_out = rw[0],
       r_out = regs[RR];


initial
  begin
    reg_dump_ct = 0;
    mem_dump_ct = 0;
    clock_ct    = 0;
  end


//  reset
always @ (posedge p_reset)
  begin
    for (i=0; i<16; i=i+1) regs[i] = 0;
    p_flags = 0;
    in_1    = 0;
    in_2    = 0;
    out     = 0;
    m_out   = 0;
    $display("PE \"%s\" Reset, Clock Cycle # %0d", PE_NAME, clock_ct);
  end


//  instruction cycle
always @ (posedge p_clock)
  begin

    last_out = out;            //  save OUT reg for mem op
    temp_dis = regs[RD] || 0;  //  save disable reg for mem op

    //  ALU or carry operation
    if ( ~(`alu_dis & (`alu_dis_i ^ temp_dis)) )  //  ALU/carry ops not disabled
      begin

        //  register read
        if (`car_in1 || `car_in2)  //  carry operation
          if (`car_srce) temp = `car_val;
          else           temp = `carry_f;
        else  //  ALU operation
          begin
            case (`srce_reg)
              RN: temp = n_in;
              RS: temp = s_in;
              RE:
                begin
                  temp = regs[RE] << `shift % WORD_WIDTH;
                  if (e_in) for (i=0; i<`shift%WORD_WIDTH; i=i+1) temp[i] = 1;
                  //  since Verilog doesn't allow variable part-select!!!
                end
              RW:
                begin
                  temp = regs[RW] >> `shift % WORD_WIDTH;
                  if (w_in) for (i=0; i<`shift%WORD_WIDTH; i=i+1)
                                temp[WORD_WIDTH-1-i] = 1;
                  //  since Verilog doesn't allow variable part-select!!!
                end
              //  note:  should have...
              //  RR:  temp = r_in;
              //  ...but router does not exist, but router supposed to pass
              //  carry word through, so will let temp = regs[RR], thus r_in
              //  will not work
              default temp = regs[`srce_reg];
            endcase
            out_res = `outres;  //  since cannot access bits of `outres!!!
            reg_res = `regres;  //  since cannot access bits of `regres!!!
          end

        //  operation execution
        if (`car_in1 || `car_in2)  //  carry operation
          for (i=0; i<WORD_WIDTH; i=i+1)
            temp[i+1] =   (in_1[i] ^ `car_nin1) & `car_in1 & temp[i]
                        | (in_2[i] ^ `car_nin2) & `car_in2 & temp[i]
                        | (in_1[i] ^ `car_nin1) & `car_in1 &
                          (in_2[i] ^ `car_nin2) & `car_in2 ;
        else  //  ALU operation
          for (i=0; i<WORD_WIDTH; i=i+1)
            begin
              out[i]  = out_res[{in_1[i], in_2[i], temp[i]}];
              temp[i] = reg_res[{in_1[i], in_2[i], temp[i]}];
            end

        //  register writeback and flag setup
        if (`car_in1 || `car_in2)  //  carry operation
          begin
            regs[RR] = temp;
            `carry_f = temp[WORD_WIDTH];
          end
        else
          begin
            regs[`dest_reg] = temp;
            `disable_f      = regs[RD] || 0;
            `out_zer_f      = !out;
            `out_msb_f      = out[WORD_WIDTH-1];
            `reg_zer_f      = !temp[WORD_WIDTH-1:0];
            `reg_msb_f      = temp[WORD_WIDTH-1];
          end

      end  //  of ALU or carry operation

    //  memory operation
    if ( ~(`mb_dis & (`mb_dis_i ^ temp_dis)) )    //  memory ops not disabled
      begin
        if (`mb_srce) temp = mem[`mb_addr];       //  `mb_srce == memory
        else
          begin
            temp = last_out;                      //  `mb_srce == OUT register
            if (`mb_d_mem) mem[`mb_addr] = temp;  //  disallow mem to mem op
          end
        if (`mb_d_in2)
            begin
              in_2       = temp;
              `in2_zer_f = !in_2;
              `in2_msb_f = in_2[WORD_WIDTH-1];
            end
        if (`mb_d_in1)
            begin
              in_1       = temp;
              `in1_zer_f = !in_1;
              `in1_msb_f = in_1[WORD_WIDTH-1];
            end
      end

    clock_ct = clock_ct + 1;

  end  //  of instruction cycle


//  memory access
always @ (posedge m_clock)
  if (m_write) mem[m_addr] = m_in;
  else               m_out = mem[m_addr];


//  register dump
always @ (posedge dump_reg)
  begin
    $display("PE \"%s\" Port and Register Dump # %0d, Clock Cycle # %0d",
             PE_NAME, reg_dump_ct, clock_ct);
    reg_dump_ct = reg_dump_ct + 1;
    $display("  PE_INSTR: mb_addr");
    $display("             %b", `mb_addr);
    $display("            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1");
    $display("               %b        %b         %b         %b",
                         `mb_srce, `mb_d_mem, `mb_d_in2, `mb_d_in1);
    $display("            srce_reg  shift  reg_res  dest_reg  out_res");
    $display("              %b   %b  %b   %b    %b",
                         `srce_reg, `shift, `regres, `dest_reg, `outres);
    $display("            car_in1  car_in2  car_nin1  car_nin2  car_srce  car_val");
    $display("               %b        %b        %b         %b         %b         %b",
             `car_in1, `car_in2, `car_nin1, `car_nin2, `car_srce, `car_val);
    $display("            alu_dis  alu_dis_i  mb_dis  mb_dis_i  (p)");
    $display("               %b         %b        %b        %b",
                         `alu_dis, `alu_dis_i, `mb_dis, `mb_dis_i);
    $write  ("     FLAGS: reg<0  reg=0  out<0  out=0  in2<0");
      $display("  in2=0  in1<0  in1=0");
    $write  ("              %b      %b      %b      %b      %b",
              `reg_msb_f, `reg_zer_f, `out_msb_f, `out_zer_f, `in2_msb_f);
      $display("      %b      %b      %b", `in2_zer_f, `in1_msb_f, `in1_zer_f);
    $display("            disab  carry  (r)");
    $display("              %b      %b", `disable_f, `carry_f);
    $display("       IN1: %b (r)", in_1);
    $display("       IN2: %b (r)", in_2);
    $display("       OUT: %b (r)", out);
    $display("        R0: %b (r)", regs[R0]);
    $display("        R1: %b (r)", regs[R1]);
    $display("        R2: %b (r)", regs[R2]);
    $display("        R3: %b (r)", regs[R3]);
    $display("        R4: %b (r)", regs[R4]);
    $display("        R5: %b (r)", regs[R5]);
    $display("        R6: %b (r)", regs[R6]);
    $display("        R7: %b (r)", regs[R7]);
    $display("        R8: %b (r)", regs[R8]);
    $display("        R9: %b (r)", regs[R9]);
    $display("   DISABLE: %b (r)", regs[RD]);
    $display("    ROUTER: %b (r)", regs[RR]);
    $display("      R_IN: %b (p/r)", r_in);
    $display("           Note reading from R_IN is really reading from ROUTER!");
    $display("     NORTH: %b (r)", regs[RN]);
    $display("      N_IN: %b (p)", n_in);
    $display("     SOUTH: %b (r)", regs[RS]);
    $display("      S_IN: %b (p)", s_in);
    $display("      EAST: %b (r)   E_IN: %b (p)", regs[RE], e_in);
    $display("      W_IN: %b (p)   WEST: %b (r)", w_in, regs[RW]);
  end


//  memory dump
always @ (posedge dump_mem)
  begin
    $display("PE \"%s\" Memory Dump # %0d, Clock Clycle # %0d", 
             PE_NAME, mem_dump_ct, clock_ct);
    mem_dump_ct = mem_dump_ct + 1;
    i = 32/(WORD_WIDTH/4);
    if (i == 0) i = 1;
    r = 0;
    for (k=0; k<MEM_LENGTH; k=k+i)
      begin
        $write("  %h: ",r);
        for (j=0; j<i; j=j+1) $write(" %h",mem[r+j]);
        $display;
        r = r + i;
      end
  end


endmodule // pe3



//\\//\\//\\//\\//\\//\\//\\//\\//\\

//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\



module pe4 // adds selectable-destination to carry unit, selectable source to
           // east & west regs, renamed working regs and reorganized pe3
  (p_clock, p_reset, p_instr, p_flags,
   n_in, s_in, e_in, w_in, r_in, 
   n_out, s_out, e_out, w_out, r_out,
   m_clock, m_write, m_addr, m_in, m_out,
   dump_reg, dump_mem);

parameter // Defaults, should be overridden by instantiating module:
  ADDR_WIDTH  = 10,           //  width of PE memory address, in bits
  WORD_WIDTH  = 32,           //  width of PE data word, in bits
  MEM_LENGTH  = 1024,         //  length of PE memory, in words
  PE_NAME     = "undefined";  //  name of PE for dump identification

input // (1 bit wide)
  p_clock, p_reset,     //  PE clock & reset, rising-edge triggered
  e_in, w_in,           //  east (lsb) & west (msb) communication
  m_clock,              //  PE memory clock for external access, rising-edge
  m_write,              //  PE memory read/write control for external access:
                        //    read = 0, write = 1
  dump_reg, dump_mem;   //  PE register & memory dump clocks, rising-edge
input  [ADDR_WIDTH-1:0] 
  m_addr;               //  PE memory address for external access
input  [WORD_WIDTH-1:0]
  n_in, s_in, r_in,     //  PE north & south & router (word) communication
  m_in;                 //  PE memory data for external access
input  [ADDR_WIDTH+46-1:0] 
  p_instr;              //  PE microinstruction (described below)
output // (1-bit wide)
  e_out, w_out;         //  east (msb) & west (lsb) communication
output [9:0] 
  p_flags;              //  PE condition flags (described below)
output [WORD_WIDTH-1:0] 
  n_out, s_out, r_out,  //  PE north & south & router (word) communication
  m_out;                //  PE memory data for external access

reg do_mem_op; // (1 bit wide)
reg [7:0] reg_op, out_op;
reg [9:0] p_flags;
reg [ADDR_WIDTH-1:0] r;
reg [WORD_WIDTH-1:0] mem[0:MEM_LENGTH-1],
                     regs[0:15],
                     in_1, in_2, out, m_out,
                     mem_wrk, alu_wrk;
reg [WORD_WIDTH:0] car_wrk;
wire e_out, w_out; // (1 bit wide)
wire [WORD_WIDTH-1:0] re, rw;
integer i, j, k, reg_dump_ct, mem_dump_ct, clock_ct;

//  PE microinstruction field definitions and content parameters:
`define   mb_addr p_instr[ADDR_WIDTH+46-1:46]  //  memory bus transfer address
`define   mb_srce p_instr[45]  //  mem bus transfer source is mem (1) or OUT (0)
`define  mb_d_mem p_instr[44]  //  memory bus transfer dest is memory, 1=true
`define  mb_d_in2 p_instr[43]  //  memory bus transfer dest is IN2, 1=true
`define  mb_d_in1 p_instr[42]  //  memory bus transfer dest is IN1, 1=true
  //  Note:  A carry-word is computed using registers IN1 and/or IN2 and a
  //  specified carry-in bit.  A carry operation is implied by specifying the
  //  registers to use, and since the carry-word is placed into the destination
  //  register, that ALU is disabled.  The carry-out is placed in the carry
  //  flag of the p_flags register, which remains unchanged by ALU operations.
`define   car_in1 p_instr[41]  //  use IN1 in carry-word computation, 1=true
`define   car_in2 p_instr[40]  //  use IN2 in carry-word computation, 1=true
`define  car_nin1 p_instr[39]  //  use inverse of IN1 (if used), 1=true
`define  car_nin2 p_instr[38]  //  use inverse of IN2 (if used), 1=true
`define  car_srce p_instr[37]  //  use value for carry-in (or carry flag) 1=true
`define   car_val p_instr[36]  //  carry-in value (if used), 1 or 0
`define  srce_reg p_instr[35:32]  //  source register of ALU operation...
`define   ew_srce p_instr[31:30]  //  source of east or west shifted-in bit...
  //  mnemonics for ew_srce values:
  parameter EW0  = 2'b00,  //  shift constant 0 into east or west register
            EW1  = 2'b01,  //  shift constant 1 into east or west register
            EWIN = 2'b10,  //  shift input port bit into east or west register 
            EWOU = 2'b11;  //  shift output port bit into east or west register
`define     shift p_instr[29:24]  //  shift east or west source reg "shift" bits
`define     regop p_instr[23:16]  //  ALU operand for dest register result
`define  dest_reg p_instr[15:12]  //  destination register of ALU operation...
`define     outop p_instr[11:4]   //  ALU operand for OUT register result
  //  mnemonics for srce_reg and dest_reg values:
  parameter R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
            R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
            R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
            RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111;
`define   alu_dis p_instr[3]  //  allow disabling of ALU operation, 1=true
`define alu_dis_i p_instr[2]  //  invert PE disable bit for ALU op, 1=true
`define    mb_dis p_instr[1]  //  allow disabling of memory bus operation....
`define  mb_dis_i p_instr[0]  //  invert PE disable bit for memory bus op....

//  PE condition flag definitions and condition register bit positions:
//    Note:  the carry flag is only affected by a carry operation.
`define reg_msb_f p_flags[9]  //  m.s.b. of destination register
`define reg_zer_f p_flags[8]  //  if destination register == 0
`define out_msb_f p_flags[7]  //  m.s.b. of register OUT
`define out_zer_f p_flags[6]  //  if register OUT == 0
`define in2_msb_f p_flags[5]  //  m.s.b. of register IN2
`define in2_zer_f p_flags[4]  //  if register IN2 == 0
`define in1_msb_f p_flags[3]  //  m.s.b. of register IN1
`define in1_zer_f p_flags[2]  //  if register IN1 == 0
`define disable_f p_flags[1]  //  state of PE disable bit
`define   carry_f p_flags[0]  //  carry-out of last carry operation

assign n_out = regs[RN],
       s_out = regs[RS],
       re    = regs[RE],  //  need since cannot access bits of regs[i]!!!
       e_out = re[WORD_WIDTH-1],
       rw    = regs[RW],  //  need since cannot access bits of regs[i]!!!
       w_out = rw[0],
       r_out = regs[RR];


//  Internal initialization program
initial
  begin
    reg_dump_ct = 0;
    mem_dump_ct = 0;
    clock_ct    = 0;
  end


//  Reset cycle program
always @ (posedge p_reset)
  begin
    for (i=0; i<16; i=i+1) regs[i] = 0;
    p_flags = 0;
    in_1    = 0;
    in_2    = 0;
    out     = 0;
    m_out   = 0;
    $display("PE \"%s\" Reset, Clock Cycle # %0d", PE_NAME, clock_ct);
  end


//  Microinstruction cycle program
always @ (posedge p_clock)
  begin

    //  Memory operation source-to-bus section
    if (~(`mb_dis & (`mb_dis_i ^ (regs[RD] || 0))))  //  not disabled
      begin
        do_mem_op = 1;  //  determine this now in case regs[RD] changes
        if (`mb_srce) mem_wrk = mem[`mb_addr];  //  `mb_srce == memory
        else          mem_wrk = out;            //  `mb_srce == OUT register
      end
    else do_mem_op = 0;

    //  ALU/carry operation section
    if (~(`alu_dis & (`alu_dis_i ^ (regs[RD] || 0))))  //  not disabled
      begin

        //  Load data sources to set up for operation
        case (`srce_reg)
          RR: alu_wrk = r_in;
          RN: alu_wrk = n_in;
          RS: alu_wrk = s_in;
          RE:
            begin
              alu_wrk = regs[RE] << `shift % WORD_WIDTH;  //  zeros shifted in
              if (   `ew_srce == EW1
                  || `ew_srce == EWIN && e_in          //  if source is a 1,
                  || `ew_srce == EWOU && e_out )       //    then "shift" it in
                for (i=0; i<`shift%WORD_WIDTH; i=i+1) alu_wrk[i] = 1;
                //  use loop since Verilog doesn't allow variable part-select!!!
            end
          RW:
            begin
              alu_wrk = regs[RW] >> `shift % WORD_WIDTH;  //  zeros shifted in
              if (   `ew_srce == EW1
                  || `ew_srce == EWIN && w_in
                  || `ew_srce == EWOU && w_out )       //  if source is a 1, 
                for (i=0; i<`shift%WORD_WIDTH; i=i+1)  //    then "shift" it in
                  alu_wrk[WORD_WIDTH-1-i] = 1;
                //  use loop since Verilog doesn't allow variable part-select!!!
            end
          default: alu_wrk = regs[`srce_reg];
        endcase
        if (`car_srce) car_wrk = `car_val;
        else           car_wrk = `carry_f;
        reg_op = `regop;  //  needed since cannot access bits of `regop!!!
        out_op = `outop;  //  needed since cannot access bits of `outop!!!

        //  Execute operation and store results
        if (`car_in1 || `car_in2)  //  carry operation
          begin
            for (i=0; i<WORD_WIDTH; i=i+1)
              begin
                out[i]       = out_op[{in_1[i], in_2[i], alu_wrk[i]}];
                car_wrk[i+1] =  (in_1[i] ^ `car_nin1) & `car_in1 & car_wrk[i]
                              | (in_2[i] ^ `car_nin2) & `car_in2 & car_wrk[i]
                              | (in_1[i] ^ `car_nin1) & `car_in1 &
                                (in_2[i] ^ `car_nin2) & `car_in2;
              end
            regs[`dest_reg] = car_wrk;
            `carry_f   = car_wrk[WORD_WIDTH];
            `reg_zer_f = !car_wrk[WORD_WIDTH-1:0];
            `reg_msb_f = car_wrk[WORD_WIDTH-1];
          end
        else                       //  ALU operation
          begin
            for (i=0; i<WORD_WIDTH; i=i+1)
              begin
                out[i]     = out_op[{in_1[i], in_2[i], alu_wrk[i]}];
                alu_wrk[i] = reg_op[{in_1[i], in_2[i], alu_wrk[i]}];
              end
            regs[`dest_reg] = alu_wrk;
            `reg_zer_f = !alu_wrk[WORD_WIDTH-1:0];
            `reg_msb_f = alu_wrk[WORD_WIDTH-1];
          end
        `out_zer_f = !out;
        `out_msb_f = out[WORD_WIDTH-1];
        `disable_f = regs[RD] || 0;  //  ok here because wont change elsewhere

      end  //  of ALU/carry operation section

    //  Memory operation bus-to-destination section
    if (do_mem_op)  //  mem ops not disabled
      begin
        //  only latch TO memory if not latched FROM memory
        if (`mb_d_mem && !`mb_srce) mem[`mb_addr] = mem_wrk;
        if (`mb_d_in2)
          begin
            in_2       = mem_wrk;
            `in2_zer_f = !in_2;
            `in2_msb_f = in_2[WORD_WIDTH-1];
          end
        if (`mb_d_in1)
          begin
            in_1       = mem_wrk;
            `in1_zer_f = !in_1;
            `in1_msb_f = in_1[WORD_WIDTH-1];
          end
      end  //  of memory operation section

    clock_ct = clock_ct + 1;

  end  //  of microinstruction cycle program


//  Memory access cycle program
always @ (posedge m_clock)
  if (m_write) mem[m_addr] = m_in;
  else               m_out = mem[m_addr];


//  Register dump cycle program
always @ (posedge dump_reg)
  begin
    $display("PE \"%s\" Port and Register Dump # %0d, Clock Cycle # %0d",
             PE_NAME, reg_dump_ct, clock_ct);
    reg_dump_ct = reg_dump_ct + 1;
    $display("  PE_INSTR: mb_addr");
    $display("             %b", `mb_addr);
    $display("            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1");
    $display("               %b        %b         %b         %b",
                         `mb_srce, `mb_d_mem, `mb_d_in2, `mb_d_in1);
    $display("            car_in1  car_in2  car_nin1  car_nin2  car_srce  car_val");
    $display("               %b        %b        %b         %b         %b         %b",
                         `car_in1, `car_in2, `car_nin1, `car_nin2, `car_srce, `car_val);
    $display("            srce_reg  ew_srce  shift    reg_op  dest_reg  out_op");
    $display("              %b      %b     %b  %b   %b   %b",
                         `srce_reg, `ew_srce, `shift, `regop, `dest_reg, `outop);
    $display("            alu_dis  alu_dis_i  mb_dis  mb_dis_i  (p)");
    $display("               %b         %b        %b        %b",
                         `alu_dis, `alu_dis_i, `mb_dis, `mb_dis_i);
    $display("     FLAGS: reg<0  reg=0  out<0  out=0  in2<0  in2=0  in1<0  in1=0");
    $display("              %b      %b      %b      %b      %b      %b      %b      %b",
                          `reg_msb_f, `reg_zer_f, `out_msb_f, `out_zer_f, `in2_msb_f, `in2_zer_f, `in1_msb_f, 
`in1_zer_f);
    $display("            disab  carry  (r)");
    $display("              %b      %b", `disable_f, `carry_f);
    $display("       IN1: %b (r)", in_1);
    $display("       IN2: %b (r)", in_2);
    $display("       OUT: %b (r)", out);
    $display("        R0: %b (r)", regs[R0]);
    $display("        R1: %b (r)", regs[R1]);
    $display("        R2: %b (r)", regs[R2]);
    $display("        R3: %b (r)", regs[R3]);
    $display("        R4: %b (r)", regs[R4]);
    $display("        R5: %b (r)", regs[R5]);
    $display("        R6: %b (r)", regs[R6]);
    $display("        R7: %b (r)", regs[R7]);
    $display("        R8: %b (r)", regs[R8]);
    $display("        R9: %b (r)", regs[R9]);
    $display("   DISABLE: %b (r)", regs[RD]);
    $display("    ROUTER: %b (r)", regs[RR]);
    $display("      R_IN: %b (p)", r_in);
    $display("     NORTH: %b (r)", regs[RN]);
    $display("      N_IN: %b (p)", n_in);
    $display("     SOUTH: %b (r)", regs[RS]);
    $display("      S_IN: %b (p)", s_in);
    $display("      EAST: %b (r)   E_IN: %b (p)", regs[RE], e_in);
    $display("      W_IN: %b (p)   WEST: %b (r)", w_in, regs[RW]);
  end


//  Memory dump cycle program
always @ (posedge dump_mem)
  begin
    $display("PE \"%s\" Memory Dump # %0d, Clock Clycle # %0d", 
             PE_NAME, mem_dump_ct, clock_ct);
    mem_dump_ct = mem_dump_ct + 1;
    i = 32/(WORD_WIDTH/4);
    if (i == 0) i = 1;
    r = 0;
    for (k=0; k<MEM_LENGTH; k=k+i)
      begin
        $write("  %h: ",r);
        for (j=0; j<i; j=j+1) $write(" %h",mem[r+j]);
        $display;
        r = r + i;
      end
  end


endmodule // pe4


// end of file pe.v

// pc01-0.v
// a Verilog-XL behavioral model of a reconfigurable processor configuration
// to perform a full add with a single PE
// (highest level module; requires module pe in file pe.v)
// for Dr. W. B. Ligon, E&CE dept., Clemson U., 1992-4
// by Ken Winiecki

module pc1;

//  system parameters:
`define    ADDR_WIDTH 32               //  width of PE memory address, in bits
parameter  WORD_WIDTH  = 32,           //  width of PE word, in bits
           MEM_LENGTH  = 16,           //  length of PE memory, in words
           MHZ         = 16,           //  clock speed, in "megahertz"
           NS          = 500/MHZ,      //  clock half-period, in "nanoseconds"
           ADDR_WIDTH  = `ADDR_WIDTH;
`define M `ADDR_WIDTH'h  //  Note all this excrement with "define"s is to 
                         //  circumnavigate a Verilog-XL bug that prevents 
                         //  parameters from working as bit length specifiers!!!

//  register and wire declarations:
reg clock, reset, dump_reg, dump_mem;
reg [ADDR_WIDTH+32-1:0] instr;
wire [9:0] flags;
integer clock_ct;

//  PE instances and connections:
pe0 pe_0 (clock, reset, instr, flags, 
          0,0,0,0,0, ,,,,, 0,,,,, dump_reg, dump_mem);

defparam  //  set PE-instance parameters to system parameters:
  pe_0.ADDR_WIDTH = ADDR_WIDTH,
  pe_0.WORD_WIDTH = WORD_WIDTH,
  pe_0.MEM_LENGTH = MEM_LENGTH,
  pe_0.PE_NAME    = "PE_0";

//  PE instruction fields and bit widths:
//    mem_addr    mem_ctrl  dest_reg  src_reg  out_res  reg_res  carry  ...
//  (ADDR_WIDTH)     2          4        4        8        8       2
//    ...  alu_dis  alu_dis_s  mem_dis  mem_dis_s
//            1         1         1         1

parameter  //  PE instruction field values:
//  mem_ctrl:
  NO_OP = 2'b00,  //  no memory operation
  R_OUT = 2'b01,  //  read to memory at address from "OUT" register
  W_IN1 = 2'b10,  //  write from memory at address to "IN_1" register
  W_IN2 = 2'b11,  //  write from memory at address to "IN_2" register
//  dest_reg & srce_reg:
  R0    = 4'b0000, R1    = 4'b0001, R2    = 4'b0010, R3    = 4'b0011,
  R4    = 4'b0100, R5    = 4'b0101, R6    = 4'b0110, R7    = 4'b0111,
  R8    = 4'b1000, R9    = 4'b1001, DIS   = 4'b1010, ROUT  = 4'b1011,
  NORTH = 4'b1100, SOUTH = 4'b1101, EAST  = 4'b1110, WEST  = 4'b1111,
//  out_res & reg_res:
  IN1     = 8'b11110000, IN2     = 8'b11001100, SRC     = 8'b10101010,
  NIN1    = 8'b00001111, NIN2    = 8'b00110011, NSRC    = 8'b01010101,
  ZEROS   = 8'b00000000, ONES    = 8'b11111111,
  AND12   = 8'b11000000, OR12    = 8'b11111100, XOR12   = 8'b00111100,
  NAND12  = 8'b00111111, NOR12   = 8'b00000011, NXOR12  = 8'b11000011,
  AND1S   = 8'b10100000, OR1S    = 8'b11111010, XOR1S   = 8'b01011010,
  NAND1S  = 8'b01011111, NOR1S   = 8'b00000101, NXOR1S  = 8'b10100101,
  AND2S   = 8'b10001000, OR2S    = 8'b11101110, XOR2S   = 8'b01100110,
  NAND2S  = 8'b01110111, NOR2S   = 8'b00010001, NXOR2S  = 8'b10011001,
  AND12S  = 8'b10000000, OR12S   = 8'b11111110, XOR12S  = 8'b01111110,
  NAND12S = 8'b01111111, NOR12S  = 8'b00000001, NXOR12S = 8'b10000001,
  SUM12S  = 8'b10010110,
//  carry:
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN_1
  //  and IN_2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  C_DIS = 2'b00,  //  do not compute carry (do an ALU operation)
  C_CAR = 2'b01,  //  compute carry using carry flag for carry-in
  C_ZER = 2'b10,  //  compute carry using 0 for carry-in
  C_ONE = 2'b11,  //  compute carry using 1 for carry-in
//  alu_dis & mem_dis:
  NO  = 1'b0,  //  do not allow ALU/memory operation disabling
  YES = 1'b1,  //  allow ALU/memory operation disabling
//  alu_dis_s & mem_dis_s:
  NORM = 1'b0,  //  PE disable bit sense for ALU/memory op is normal
  INV  = 1'b1,  //  PE disable bit sense for ALU/memory op is inverted
//  for convenience when not allowing any disabling:
  ND = { NO, NORM, NO, NORM };

parameter // bit positions of PE flags:
//  Note that flags other than carry are not affected by a carry operation,
//  and the carry flag is not affected by an ALU operation.
  REG_MSB_F = 9,  //  m.s.b. of destination register
  REG_ZER_F = 8,  //  if destination register = 0
  OUT_MSB_F = 7,  //  m.s.b. of register OUT
  OUT_ZER_F = 6,  //  if register OUT = 0
  IN2_MSB_F = 5,  //  m.s.b. of register IN_2
  IN2_ZER_F = 4,  //  if register IN_2 = 0
  IN1_MSB_F = 3,  //  m.s.b. of register IN_1
  IN1_ZER_F = 2,  //  if register IN_1 = 0
  DISABLE_F = 1,  //  state of PE disable bit
    CARRY_F = 0;  //  result of last carry operation

//  Write a program in Verilog-XL to control the processing elements directly,
//  and put it in the "initial" block to execute.  Set up the PE memory.
//  Reset the PE by clocking it's p_reset line.  (Clock a line using #NS to 
//  delay each transition.)  Build a PE instruction using the above defined 
//  instruction fields and value parameters.  Clock the PEs.  Monitor the 
//  flags of a PE using the above bit position parameters.  Note:  Verilog-XL 
//  has no way of dealing realistically with "don't cares," so never allow the 
//  use of "don't knows" (undefined values)!!!
initial 
  begin
    dump_reg    = 0;
    dump_mem    = 0;
    clock       = 0;
    clock_ct    = 0;
    pe_0.mem[0] = 'hF0F0_0F0F;
    pe_0.mem[1] = 'hF0F1_8F0F;
    reset_regs;
    do({ `M 0, W_IN1, R0, R0, SRC, SRC, C_DIS, ND });
    do({ `M 1, W_IN2, R0, R0, SRC, SRC, C_DIS, ND });
    do({ `M 0, NO_OP, R0, R0, SRC, SRC, C_ZER, ND });
    do({ `M 0, NO_OP, ROUT, ROUT, SUM12S, SRC, C_DIS, ND });
    do({ `M 2, R_OUT, R0, R0, SRC, SRC, C_DIS, ND });
    form_feed;
    $display("Integer Addition, One Word Wide, One PE");
    reg_dump;
    mem_dump;
    $display("%0d clock cycles", clock_ct);
  end

task reset_regs;
  begin
    #NS reset = 1;
    #NS reset = 0;
  end
endtask

task do;
  input [ADDR_WIDTH+32-1:0] instruction;
  begin
   instr = instruction;
   #NS clock = 1;
   #NS clock = 0;
   clock_ct = clock_ct + 1;
  end
endtask

task reg_dump;
  begin
    #NS dump_reg = 1;
    #NS dump_reg = 0;
  end
endtask

task mem_dump;
  begin
    #NS dump_mem = 1;
    #NS dump_mem = 0;
  end
endtask

task form_feed;
  $write("\14");
endtask

endmodule

Host command: verilog
Command arguments:
    pe.v
    pc01-0.v

VERILOG-XL 1.6a.4 log file created Jul 14, 1994  17:09:55
  * Copyright Cadence Design Systems, Inc. 1985, 1988.    *
  *     All Rights Reserved.       Licensed Software.     *
  * Confidential and proprietary information which is the *
  *      property of Cadence Design Systems, Inc.         *
Compiling source file "pe.v"

Compiling source file "pc01-0.v"

Highest level modules:
pe
pe2
pe3
pe4
pc1

Integer Addition, One Word Wide, One PE
PE "PE_0" Binary Port and Register Dump # 0, Clock Cycle # 5
  PE_INSTR: mem_addr
            00000000000000000000000000000010
            mem_ctrl  dest_reg  srce_reg  out_res   reg_res
               01       0000      0000    10101010  10101010
            carry  alu_dis  alu_dis_s  mem_dis  mem_dis_s  (p)
              00      0         0         0         0
     FLAGS: reg<0  reg=0  out<0  out=0  in2<0  in2=0  in1<0  in1=0
              0      1      0      1      1      0      1      0
            disab  carry  (r)
              0      1
       IN1: 11110000111100000000111100001111 (r)
       IN2: 11110000111100011000111100001111 (r)
       OUT: 00000000000000000000000000000000 (r)
        R0: 00000000000000000000000000000000 (r)
        R1: 00000000000000000000000000000000 (r)
        R2: 00000000000000000000000000000000 (r)
        R3: 00000000000000000000000000000000 (r)
        R4: 00000000000000000000000000000000 (r)
        R5: 00000000000000000000000000000000 (r)
        R6: 00000000000000000000000000000000 (r)
        R7: 00000000000000000000000000000000 (r)
        R8: 00000000000000000000000000000000 (r)
        R9: 00000000000000000000000000000000 (r)
       DIS: 00000000000000000000000000000000 (r)
     R_OUT: 11100001111000000001111000011110 (r)
      R_IN: 11100001111000000001111000011110 (p/r)
     N_OUT: 00000000000000000000000000000000 (r)
      N_IN: 00000000000000000000000000000000 (p)
     S_OUT: 00000000000000000000000000000000 (r)
      S_IN: 00000000000000000000000000000000 (p)
      EAST: 00000000000000000000000000000000 (r)   E_IN: 0 (p)
      W_IN: 0 (p)   WEST: 00000000000000000000000000000000 (r)
PE "PE_0" Hexidecimal Memory Dump # 0, Clock Clycle # 5
  00000000:  f0f00f0f f0f18f0f e1e19e1e xxxxxxxx
  00000004:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  00000008:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  0000000c:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
5 clock cycles
37 warnings
860 simulation events
CPU time: 1.2 secs to compile + 0.4 secs to link + 0.2 secs in simulation
End of VERILOG-XL 1.6a.4   Jul 14, 1994  17:09:57

module pc1;

// pc01-.v
// a Verilog-XL behavioral model of a reconfigurable processor configuration
// to perform a full add with a single PE
// (highest level module; requires module pe in file pe.v)
// for Dr. W. B. Ligon, E&CE dept., Clemson U., 1992-4
// by Ken Winiecki

//  system parameters:
`define    ADDR_WIDTH 4                //  width of PE memory address, in bits
parameter  WORD_WIDTH  = 32,           //  width of PE word, in bits
           MEM_LENGTH  = 16,           //  length of PE memory, in words
           MHZ         = 16.7,         //  clock speed, in "megahertz"
           NS          = 500/MHZ,      //  clock half-period, in "nanoseconds"
           ADDR_WIDTH  = `ADDR_WIDTH;
`define M `ADDR_WIDTH'h  //  Note all this excrement with "define"s is to 
                         //  circumnavigate a Verilog-XL bug that prevents 
                         //  parameters from working as bit length specifiers!!!

//  register and wire declarations:
reg clock, reset, dump_reg, dump_mem;
reg [ADDR_WIDTH+34-1:0] instr;
wire [9:0] flags;
integer clock_ct;

//  PE instances and connections:
pe pe_0 (clock, reset, instr, flags, 
         0,0,0,0,0, ,,,,, 0,,,,, dump_reg, dump_mem);

defparam  //  set PE-instance parameters to system parameters:
  pe_0.ADDR_WIDTH = ADDR_WIDTH,
  pe_0.WORD_WIDTH = WORD_WIDTH,
  pe_0.MEM_LENGTH = MEM_LENGTH,
  pe_0.PE_NAME    = "PE_0";

//  PE instruction fields and bit widths:
//    mb_addr    mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  src_reg  reg_res ...
//  (ADDR_WIDTH)    1        1         1         1         4        8
//    ...  dest_reg  out_res  carry  alu_dis  alu_dis_s  mb_dis  mb_dis_s
//            4         8       2       1         1        1        1

parameter  //  PE instruction field values:
//  mb_addr:   memory bus transfer address
//  mb_srce:   source of memory bus transfer is ...
  OUT = 1'b0,  //  ... register "OUT"
  MEM = 1'b1,  //  ... memory
//  mb_d_mem & mb_d_in2 & mb_d_in1:  destinations of memory bus transfers
  F = 1'b0,  //  false
  T = 1'b1,  //  true
//  srce_reg & dest_reg:  destination and source registers of ALU operations
  R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
  R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
  R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
  RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111,
//  reg_res & out_res:  ALU operands for "OUT" and destination register results
  IN1     = 8'b11110000, IN2     = 8'b11001100, SRC     = 8'b10101010,
  NIN1    = 8'b00001111, NIN2    = 8'b00110011, NSRC    = 8'b01010101,
  ZEROS   = 8'b00000000, ONES    = 8'b11111111,
  AND12   = 8'b11000000, OR12    = 8'b11111100, XOR12   = 8'b00111100,
  NAND12  = 8'b00111111, NOR12   = 8'b00000011, NXOR12  = 8'b11000011,
  AND1S   = 8'b10100000, OR1S    = 8'b11111010, XOR1S   = 8'b01011010,
  NAND1S  = 8'b01011111, NOR1S   = 8'b00000101, NXOR1S  = 8'b10100101,
  AND2S   = 8'b10001000, OR2S    = 8'b11101110, XOR2S   = 8'b01100110,
  NAND2S  = 8'b01110111, NOR2S   = 8'b00010001, NXOR2S  = 8'b10011001,
  AND12S  = 8'b10000000, OR12S   = 8'b11111110, XOR12S  = 8'b01111110,
  NAND12S = 8'b01111111, NOR12S  = 8'b00000001, NXOR12S = 8'b10000001,
  SUM12S  = 8'b10010110,
//  carry:
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN_1
  //  and IN_2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  CN = 2'b00,  //  do not compute carry (do an ALU operation)
  CC = 2'b01,  //  compute carry using carry flag for carry-in
  C0 = 2'b10,  //  compute carry using 0 for carry-in
  C1 = 2'b11,  //  compute carry using 1 for carry-in
//  alu_dis & mb_dis:      allow disabling of ALU/memory bus operation; T or F
//  alu_dis_i & mb_dis_i:  invert PE disable bit for ALU/memory bus op; T or F
//  for convenience when not using memory bus:
  NMEM = { `M 0, MEM, F, F, F },
//  for convenience when not doing any ALU operations:
  NALU = { R0, SRC, R0, ZEROS },
//  for convenience when not allowing any disabling:
  NDIS = { F, F, F, F };

parameter // bit positions of PE flags:
//  Note that flags other than carry are not affected by a carry operation,
//  and the carry flag is not affected by an ALU operation.
  REG_MSB_F = 9,  //  m.s.b. of destination register
  REG_ZER_F = 8,  //  if destination register = 0
  OUT_MSB_F = 7,  //  m.s.b. of register OUT
  OUT_ZER_F = 6,  //  if register OUT = 0
  IN2_MSB_F = 5,  //  m.s.b. of register IN_2
  IN2_ZER_F = 4,  //  if register IN_2 = 0
  IN1_MSB_F = 3,  //  m.s.b. of register IN_1
  IN1_ZER_F = 2,  //  if register IN_1 = 0
  DISABLE_F = 1,  //  state of PE disable bit
    CARRY_F = 0;  //  result of last carry operation

//  Write a program in Verilog-XL to control the processing elements directly,
//  and put it in the "initial" block to execute.  Set up the PE memory.
//  Reset the PE by clocking it's p_reset line.  (Clock a line using #NS to 
//  delay each transition.)  Build a PE instruction using the above defined 
//  instruction fields and value parameters.  Clock the PEs.  Monitor the 
//  flags of a PE using the above bit position parameters.  Note:  Verilog-XL 
//  has no way of dealing realistically with "don't cares," so never allow the 
//  use of "don't knows" (undefined values)!!!
initial 
  begin
    form_feed;
    $display("Integer Addition, One Word Wide, One PE");
    dump_reg    = 0;
    dump_mem    = 0;
    clock       = 0;
    clock_ct    = 0;
    pe_0.mem[0] = 'hF0F0_0F0F;
    pe_0.mem[1] = 'hF0F1_8F0F;
    reset_regs;
    do({ `M 0, MEM, F, F, T, NALU, CN, NDIS });
    do({ `M 1, MEM, F, T, F, NALU, CN, NDIS });
    do({ NMEM, NALU, C0, NDIS });
    do({ NMEM, RR, SRC, RR, SUM12S, CN, NDIS });
    do({ `M 2, OUT, T, F, F, NALU, CN, NDIS });
    reg_dump;
    mem_dump;
    $display("%0d clock cycles", clock_ct);
  end

task reset_regs;
  begin
    #NS reset = 1;
    #NS reset = 0;
  end
endtask

task do;
  input [ADDR_WIDTH+34-1:0] instruction;
  begin
   instr = instruction;
   #NS clock = 1;
   #NS clock = 0;
   clock_ct = clock_ct + 1;
  end
endtask

task reg_dump;
  begin
    #NS dump_reg = 1;
    #NS dump_reg = 0;
  end
endtask

task mem_dump;
  begin
    #NS dump_mem = 1;
    #NS dump_mem = 0;
  end
endtask

task form_feed;
  $write("\14");
endtask

endmodule

Host command: verilog
Command arguments:
    pe.v
    pc01-.v

VERILOG-XL 1.6a.4 log file created Jul 14, 1994  17:09:55
  * Copyright Cadence Design Systems, Inc. 1985, 1988.    *
  *     All Rights Reserved.       Licensed Software.     *
  * Confidential and proprietary information which is the *
  *      property of Cadence Design Systems, Inc.         *
Compiling source file "pe.v"

Compiling source file "pc01-.v"

Highest level modules:
pe
pe2
pe3
pe4
pc1

Integer Addition, One Word Wide, One PE
PE "PE_0" Reset, Clock Cycle # 0
PE "PE_0" Port and Register Dump # 0, Clock Cycle # 5
  PE_INSTR: mb_addr
            0010
            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  srce_reg  reg_res  dest_reg
               0        1         0         0        0000    10101010   0000
            out_res  carry  alu_dis  alu_dis_i  mb_dis  mb_dis_i  (p)
            00000000   00      0         0        0        0
     FLAGS: reg<0  reg=0  out<0  out=0  in2<0  in2=0  in1<0  in1=0
              0      1      0      1      1      0      1      0
            disab  carry  (r)
              0      1
       IN1: 11110000111100000000111100001111 (r)
       IN2: 11110000111100011000111100001111 (r)
       OUT: 00000000000000000000000000000000 (r)
        R0: 00000000000000000000000000000000 (r)
        R1: 00000000000000000000000000000000 (r)
        R2: 00000000000000000000000000000000 (r)
        R3: 00000000000000000000000000000000 (r)
        R4: 00000000000000000000000000000000 (r)
        R5: 00000000000000000000000000000000 (r)
        R6: 00000000000000000000000000000000 (r)
        R7: 00000000000000000000000000000000 (r)
        R8: 00000000000000000000000000000000 (r)
        R9: 00000000000000000000000000000000 (r)
   DISABLE: 00000000000000000000000000000000 (r)
    ROUTER: 11100001111000000001111000011110 (r)
      R_IN: 11100001111000000001111000011110 (p/r)
     NORTH: 00000000000000000000000000000000 (r)
      N_IN: 00000000000000000000000000000000 (p)
     SOUTH: 00000000000000000000000000000000 (r)
      S_IN: 00000000000000000000000000000000 (p)
      EAST: 00000000000000000000000000000000 (r)   E_IN: 0 (p)
      W_IN: 0 (p)   WEST: 00000000000000000000000000000000 (r)
PE "PE_0" Memory Dump # 0, Clock Clycle # 5
  0:  f0f00f0f f0f18f0f e1e19e1e xxxxxxxx
  4:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  8:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  c:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
5 clock cycles
37 warnings
889 simulation events
CPU time: 1.3 secs to compile + 0.4 secs to link + 0.2 secs in simulation
End of VERILOG-XL 1.6a.4   Jul 14, 1994  18:07:43

// pc02-0.v
// a Verilog-XL behavioral model of a reconfigurable processor configuration
// to perform a shift-add multiply with one PE
// (highest level module; requires module pe in file pe.v)
// for Dr. W. B. Ligon, E&CE dept., Clemson U., 1992-4
// by Ken Winiecki

module pc2;

//  system parameters:
`define    ADDR_WIDTH 32               //  width of PE memory address, in bits
parameter  WORD_WIDTH  = 16,           //  width of PE word, in bits
           MEM_LENGTH  = 16,           //  length of PE memory, in words
           MHZ         = 16,           //  clock speed, in "megahertz"
           NS          = 500/MHZ,      //  clock half-period, in "nanoseconds"
           ADDR_WIDTH  = `ADDR_WIDTH;
`define A `ADDR_WIDTH'h  //  Note all this excrement with "define"s is to 
                         //  circumnavigate a Verilog-XL bug that prevents 
                         //  parameters from working as bit length specifiers!!!

//  variable declarations:
reg clock, reset, w_in_0, dump_r_0, dump_m_0, save1;
reg [ADDR_WIDTH+32-1:0] instr_0;
wire w_out_0;
wire [9:0] flags_0;
integer clock_ct;

//  PE instances and connections:
pe0 pe_0 (clock, reset, instr_0, flags_0, 
          0,0,0,w_in_0,0, ,,,w_out_0,, 0,,,,, dump_r_0, dump_m_0);

defparam  //  set PE-instance parameters to system parameters:
  pe_0.ADDR_WIDTH = ADDR_WIDTH,
  pe_0.WORD_WIDTH = WORD_WIDTH,
  pe_0.MEM_LENGTH = MEM_LENGTH,
  pe_0.PE_NAME    = "PE_0";

//  PE instruction fields and bit widths:
//    mem_addr    mem_ctrl  dest_reg  src_reg  out_res  reg_res  carry  ...
//  (ADDR_WIDTH)     2          4        4        8        8       2
//    ...  alu_dis  alu_dis_s  mem_dis  mem_dis_s
//            1         1         1         1

parameter  //  PE instruction field values:
//  mem_ctrl:
  NO_OP = 2'b00,  //  no memory operation
  R_OUT = 2'b01,  //  read to memory at address from "OUT" register
  W_IN1 = 2'b10,  //  write from memory at address to "IN_1" register
  W_IN2 = 2'b11,  //  write from memory at address to "IN_2" register
//  dest_reg & srce_reg:
  R0    = 4'b0000, R1    = 4'b0001, R2    = 4'b0010, R3    = 4'b0011,
  R4    = 4'b0100, R5    = 4'b0101, R6    = 4'b0110, R7    = 4'b0111,
  R8    = 4'b1000, R9    = 4'b1001, DIS   = 4'b1010, ROUT  = 4'b1011,
  NORTH = 4'b1100, SOUTH = 4'b1101, EAST  = 4'b1110, WEST  = 4'b1111,
//  out_res & reg_res:
  IN1     = 8'b11110000, IN2     = 8'b11001100, SRC     = 8'b10101010,
  NIN1    = 8'b00001111, NIN2    = 8'b00110011, NSRC    = 8'b01010101,
  ZEROS   = 8'b00000000, ONES    = 8'b11111111,
  AND12   = 8'b11000000, OR12    = 8'b11111100, XOR12   = 8'b00111100,
  NAND12  = 8'b00111111, NOR12   = 8'b00000011, NXOR12  = 8'b11000011,
  AND1S   = 8'b10100000, OR1S    = 8'b11111010, XOR1S   = 8'b01011010,
  NAND1S  = 8'b01011111, NOR1S   = 8'b00000101, NXOR1S  = 8'b10100101,
  AND2S   = 8'b10001000, OR2S    = 8'b11101110, XOR2S   = 8'b01100110,
  NAND2S  = 8'b01110111, NOR2S   = 8'b00010001, NXOR2S  = 8'b10011001,
  AND12S  = 8'b10000000, OR12S   = 8'b11111110, XOR12S  = 8'b01111110,
  NAND12S = 8'b01111111, NOR12S  = 8'b00000001, NXOR12S = 8'b10000001,
  SUM12S  = 8'b10010110,
//  carry:
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN_1
  //  and IN_2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  C_DIS = 2'b00,  //  do not compute carry (do an ALU operation)
  C_CAR = 2'b01,  //  compute carry using carry flag for carry-in
  C_ZER = 2'b10,  //  compute carry using 0 for carry-in
  C_ONE = 2'b11,  //  compute carry using 1 for carry-in
//  alu_dis & mem_dis:
  NO  = 1'b0,  //  do not allow ALU/memory operation disabling
  YES = 1'b1,  //  allow ALU/memory operation disabling
//  alu_dis_s & mem_dis_s:
  NORM = 1'b0,  //  PE disable bit sense for ALU/memory op is normal
  INV  = 1'b1,  //  PE disable bit sense for ALU/memory op is inverted
//  for convenience when not allowing any disabling:
  ND = { NO, NORM, NO, NORM };

parameter // bit positions of PE flags
//  Note that flags other than carry are not affected by a carry operation,
//  and the carry flag is not affected by an ALU operation.
  REG_MSB_F = 9,  //  m.s.b. of destination register
  REG_ZER_F = 8,  //  if destination register = 0
  OUT_MSB_F = 7,  //  m.s.b. of register OUT
  OUT_ZER_F = 6,  //  if register OUT = 0
  IN2_MSB_F = 5,  //  m.s.b. of register IN_2
  IN2_ZER_F = 4,  //  if register IN_2 = 0
  IN1_MSB_F = 3,  //  m.s.b. of register IN_1
  IN1_ZER_F = 2,  //  if register IN_1 = 0
  DISABLE_F = 1,  //  state of PE disable bit
    CARRY_F = 0;  //  result of last carry operation

//  Write a program in Verilog-XL to control the processing elements directly,
//  and put it in the "initial" block to execute.  Set up the PE memory.
//  Reset the PE by clocking it's p_reset line.  (Clock a line using #NS to 
//  delay each transition.)  Build a PE instruction using the above defined 
//  instruction fields and value parameters.  Clock the PEs.  Monitor the 
//  flags of a PE using the above bit position parameters.  Note:  Verilog-XL 
//  has no way of dealing realistically with "don't cares," so never allow the 
//  use of "don't knows" (undefined values)!!!
initial 
  begin
    w_in_0      = 0;
    dump_r_0    = 0;
    dump_m_0    = 0;
    clock       = 0;
    clock_ct    = 0;
    pe_0.mem[0] = 0;
    pe_0.mem[1] = pe_0.mem[0] - 1;
    pe_0.mem[2] = pe_0.mem[0] - 1;
    reset_regs;

    // in_1 = mem[1]:
    do({ `A 1, W_IN1, R0, R0, ZEROS, SRC, C_DIS, ND });
    // in_2 = mem[2]:
    do({ `A 2, W_IN2, R0, R0, ZEROS, SRC, C_DIS, ND });
    // west = in_1, in_1 = 0:
    do({ `A 0, W_IN1, WEST, R0, ZEROS, IN1, C_DIS, ND });
    repeat (WORD_WIDTH)
      begin
        // r0 = west rotated right:
        w_in_0 = w_out_0;
        do({ `A 0, NO_OP, R0, WEST, ZEROS, SRC, C_DIS, ND });
        if (flags_0[REG_MSB_F]) // compute new unshifted partial sum & carry
          begin
            // compute carry for in_1 + in_2:
            do({ `A 0, NO_OP, R0, R0, ZEROS, SRC, C_ZER, ND });
            // west = in_1 + in_2:
            do({ `A 0, NO_OP, WEST, ROUT, ZEROS, SUM12S, C_DIS, ND });
            w_in_0 = flags_0[CARRY_F];
          end
        else // use previous unshifted partial sum & 0 carry
          begin
            // west = in_1:
            do({ `A 0, NO_OP, WEST, ROUT, ZEROS, IN1, C_DIS, ND });
            w_in_0 = 0;
          end
        // out = west shifted right with carry shifted in:
        do({ `A 0, NO_OP, R2, WEST, SRC, ZEROS, C_DIS, ND });
        // save lsb of west:
        save1 = w_out_0;
        // mem[3] = out, west = r1:
        do({ `A 3, R_OUT, WEST, R1, ZEROS, SRC, C_DIS, ND });
        // r1 = west shifted right with saved bit shifted in, in_1 = mem[3]:
        w_in_0 = save1;
        do({ `A 3, W_IN1, R1, WEST, ZEROS, SRC, C_DIS, ND });
        // west = r0:
        do({ `A 0, NO_OP, WEST, R0, ZEROS, SRC, C_DIS, ND });
      end
    // out = r1:
    do({ `A 0, NO_OP, R1, R1, SRC, SRC, C_DIS, ND });
    // mem[4] = out:
    do({ `A 4, R_OUT, R0, R0, ZEROS, SRC, C_DIS, ND });

    form_feed;
    $display("Integer Multiplication, One Word Operands, One PE");
    r_0_dump;
    m_0_dump;
    $display("%0d x %0d = %0d x ... + %0d", pe_0.mem[1], pe_0.mem[2], 
             pe_0.mem[3], pe_0.mem[4]);
    $display("%0d clock cycles", clock_ct);
  end

task reset_regs;
  begin
    #NS reset = 1;
    #NS reset = 0;
  end
endtask

task do;
  input [ADDR_WIDTH+32-1:0] i_0;
  begin
   instr_0 = i_0;
   #NS clock = 1;
   #NS clock = 0;
   clock_ct = clock_ct + 1;
  end
endtask

task r_0_dump;
  begin
    #NS dump_r_0 = 1;
    #NS dump_r_0 = 0;
  end
endtask

task m_0_dump;
  begin
    #NS dump_m_0 = 1;
    #NS dump_m_0 = 0;
  end
endtask

task form_feed;
  $write("\14");
endtask

endmodule

Host command: verilog
Command arguments:
    pe.v
    pc02-0.v

VERILOG-XL 1.6a.4 log file created Jul 14, 1994  19:09:48
  * Copyright Cadence Design Systems, Inc. 1985, 1988.    *
  *     All Rights Reserved.       Licensed Software.     *
  * Confidential and proprietary information which is the *
  *      property of Cadence Design Systems, Inc.         *
Compiling source file "pe.v"

Compiling source file "pc02-0.v"

Highest level modules:
pe
pe2
pe3
pe4
pc2

Integer Multiplication, One Word Operands, One PE
PE "PE_0" Binary Port and Register Dump # 0, Clock Cycle # 117
  PE_INSTR: mem_addr
            00000000000000000000000000000100
            mem_ctrl  dest_reg  srce_reg  out_res   reg_res
               01       0000      0000    00000000  10101010
            carry  alu_dis  alu_dis_s  mem_dis  mem_dis_s  (p)
              00      0         0         0         0
     FLAGS: reg<0  reg=0  out<0  out=0  in2<0  in2=0  in1<0  in1=0
              1      0      0      1      1      0      1      1
            disab  carry  (r)
              0      1
       IN1: 1111111111111110 (r)
       IN2: 1111111111111111 (r)
       OUT: 0000000000000000 (r)
        R0: 1111111111111111 (r)
        R1: 0000000000000001 (r)
        R2: 0000000000000000 (r)
        R3: 0000000000000000 (r)
        R4: 0000000000000000 (r)
        R5: 0000000000000000 (r)
        R6: 0000000000000000 (r)
        R7: 0000000000000000 (r)
        R8: 0000000000000000 (r)
        R9: 0000000000000000 (r)
       DIS: 0000000000000000 (r)
     R_OUT: 0000000000000000 (r)
      R_IN: 1111111111111110 (p/r)
     N_OUT: 0000000000000000 (r)
      N_IN: 0000000000000000 (p)
     S_OUT: 0000000000000000 (r)
      S_IN: 0000000000000000 (p)
      EAST: 0000000000000000 (r)   E_IN: 0 (p)
      W_IN: 0 (p)   WEST: 1111111111111111 (r)
PE "PE_0" Hexidecimal Memory Dump # 0, Clock Clycle # 117
  0000:  0000 ffff ffff fffe 0001 xxxx xxxx xxxx
  0008:  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
65535 x 65535 = 65534 x ... + 1
117 clock cycles
39 warnings
10342 simulation events
CPU time: 1.4 secs to compile + 0.4 secs to link + 1.5 secs in simulation
End of VERILOG-XL 1.6a.4   Jul 14, 1994  19:09:52

module pc2;

// pc02-.v
// a Verilog-XL behavioral model of a reconfigurable processor configuration
// for a 2's-complement integer shift-add 1x1=2 word multiply with 1 PE
// (highest level module; requires module pe in file pe.v)
// for Dr. W. B. Ligon, E&CE dept., Clemson U., 1992-4
// by Ken Winiecki

//  system parameters:
`define    ADDR_WIDTH 4                //  width of PE memory address, in bits
parameter  WORD_WIDTH  = 32,           //  width of PE word, in bits
           MEM_LENGTH  = 16,           //  length of PE memory, in words
           MHZ         = 16.7,         //  clock speed, in "megahertz"
           NS          = 500/MHZ,      //  clock half-period, in "nanoseconds"
           ADDR_WIDTH  = `ADDR_WIDTH;
`define M `ADDR_WIDTH'h  //  Note all this excrement with "define"s is to 
                         //  circumnavigate a Verilog-XL bug that prevents 
                         //  parameters from working as bit length specifiers!!!

//  variable declarations:
reg clock, reset, w_in_0, dump_r_0, dump_m_0, saved1, negative;
reg [WORD_WIDTH-1:0] single;
reg [WORD_WIDTH+WORD_WIDTH-1:0] double;
reg [ADDR_WIDTH+34-1:0] instr_0;
wire w_out_0;
wire [9:0] flags_0;
integer clock_ct;

//  PE instances and connections:
pe pe_0 (clock, reset, instr_0, flags_0, 
         0,0,0,w_in_0,0, ,,,w_out_0,, 0,,,,, dump_r_0, dump_m_0);

defparam  //  set PE-instance parameters to system parameters:
  pe_0.ADDR_WIDTH = ADDR_WIDTH,
  pe_0.WORD_WIDTH = WORD_WIDTH,
  pe_0.MEM_LENGTH = MEM_LENGTH,
  pe_0.PE_NAME    = "PE_0";

//  PE instruction fields and bit widths:
//    mb_addr    mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  src_reg  reg_res ...
//  (ADDR_WIDTH)    1        1         1         1         4        8
//    ...  dest_reg  out_res  carry  alu_dis  alu_dis_s  mb_dis  mb_dis_s
//            4         8       2       1         1        1        1

parameter  //  PE instruction field values:
//  mb_addr:   memory bus transfer address
//  mb_srce:   source of memory bus transfer is ...
  OUT = 1'b0,  //  ... register "OUT"
  MEM = 1'b1,  //  ... memory
//  mb_d_mem & mb_d_in2 & mb_d_in1:  destinations of memory bus transfers
  F = 1'b0,  //  false
  T = 1'b1,  //  true
//  srce_reg & dest_reg:  destination and source registers of ALU operations
  R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
  R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
  R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
  RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111,
//  reg_res & out_res:  ALU operands for "OUT" and destination register results
  IN1     = 8'b11110000, IN2     = 8'b11001100, SRC     = 8'b10101010,
  NIN1    = 8'b00001111, NIN2    = 8'b00110011, NSRC    = 8'b01010101,
  ZEROS   = 8'b00000000, ONES    = 8'b11111111,
  AND12   = 8'b11000000, OR12    = 8'b11111100, XOR12   = 8'b00111100,
  NAND12  = 8'b00111111, NOR12   = 8'b00000011, NXOR12  = 8'b11000011,
  AND1S   = 8'b10100000, OR1S    = 8'b11111010, XOR1S   = 8'b01011010,
  NAND1S  = 8'b01011111, NOR1S   = 8'b00000101, NXOR1S  = 8'b10100101,
  AND2S   = 8'b10001000, OR2S    = 8'b11101110, XOR2S   = 8'b01100110,
  NAND2S  = 8'b01110111, NOR2S   = 8'b00010001, NXOR2S  = 8'b10011001,
  AND12S  = 8'b10000000, OR12S   = 8'b11111110, XOR12S  = 8'b01111110,
  NAND12S = 8'b01111111, NOR12S  = 8'b00000001, NXOR12S = 8'b10000001,
  SUM12S  = 8'b10010110,
//  carry:
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN_1
  //  and IN_2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  CN = 2'b00,  //  do not compute carry (do an ALU operation)
  CC = 2'b01,  //  compute carry using carry flag for carry-in
  C0 = 2'b10,  //  compute carry using 0 for carry-in
  C1 = 2'b11,  //  compute carry using 1 for carry-in
//  alu_dis & mb_dis:      allow disabling of ALU/memory bus operation; T or F
//  alu_dis_i & mb_dis_i:  invert PE disable bit for ALU/memory bus op; T or F
//  for convenience when not using memory bus:
  NMEM = { `M 0, MEM, F, F, F },
//  for convenience when not doing any ALU operations:
  NALU = { R0, SRC, R0, ZEROS },
//  for convenience when not allowing any disabling:
  NDIS = { F, F, F, F },
//  for convenience when squandering clock cycles:
  NOOP = { NMEM, NALU, CN, NDIS };

parameter // bit positions of PE flags
//  Note that flags other than carry are not affected by a carry operation,
//  and the carry flag is not affected by an ALU operation.
  REG_MSB_F = 9,  //  m.s.b. of destination register
  REG_ZER_F = 8,  //  if destination register = 0
  OUT_MSB_F = 7,  //  m.s.b. of register OUT
  OUT_ZER_F = 6,  //  if register OUT = 0
  IN2_MSB_F = 5,  //  m.s.b. of register IN_2
  IN2_ZER_F = 4,  //  if register IN_2 = 0
  IN1_MSB_F = 3,  //  m.s.b. of register IN_1
  IN1_ZER_F = 2,  //  if register IN_1 = 0
  DISABLE_F = 1,  //  state of PE disable bit
    CARRY_F = 0;  //  result of last carry operation

//  Write a program in Verilog-XL to control the processing elements directly,
//  and put it in the "initial" block to execute.  Set up the PE memory.
//  Reset the PE by clocking it's p_reset line.  (Clock a line using #NS to 
//  delay each transition.)  Build a PE instruction using the above defined 
//  instruction fields and value parameters.  Clock the PEs.  Monitor the 
//  flags of a PE using the above bit position parameters.  Note:  Verilog-XL 
//  has no way of dealing realistically with "don't cares," so never allow the 
//  use of "don't knows" (undefined values)!!!
initial 
  begin
    form_feed;
    $display("2's-complement Integer 1x1=2-word Multiply with 1 PE");
    single      = -1;
    double      = single + 1;
    w_in_0      = 0;
    dump_r_0    = 0;
    dump_m_0    = 0;
    clock       = 0;
    clock_ct    = 0;
    negative    = 0;
    pe_0.mem[0] = -1;
    pe_0.mem[1] = 1;

    //   clear PE registers
    reset_regs;
    //   put mem[0] into in_2
    do({ `M 0, MEM, F, T, F, NALU, CN, NDIS });
    //   start adjusting for sign of in_2
    sign_stuff;
    //   west = in_1(=0) + in_2 + c, put mem[1] into in_2
    do({ `M 1, MEM, F, T, F, RR, SUM12S, RW, ZEROS, CN, NDIS });
    //   start adjusting for sign of in_2
    sign_stuff;
    //   out = in_1(=0) + in_2 + c
    do({ NMEM, RR, ZEROS, RR, SUM12S, CN, NDIS });
    //   put out into in_2
    do({ `M 0, OUT, F, T, F, NALU, CN, NDIS });

    repeat (WORD_WIDTH)
      begin
        //   r0 = west rotated right
        w_in_0 = w_out_0; do({ NMEM, RW, SRC, R0, ZEROS, CN, NDIS });
        if (flags_0[REG_MSB_F]) // MSB of right-rotated operand is 1
          begin // compute new unshifted partial sum & carry
            //   compute carry for in_1 + in_2
            do({ NMEM, NALU, C0, NDIS });
            //   west = in_1 + in_2, west_in = carry
            do({ NMEM, RR, SUM12S, RW, ZEROS, CN, NDIS });
            w_in_0 = flags_0[CARRY_F];
          end
        else // MSB of right-rotated operand is 0
          begin // use previous unshifted partial sum & 0 carry
            //   filler cycle
            do({ NOOP });
            //   west = in_1, west_in = 0;
            do({ NMEM, RW, IN1, RW, ZEROS, CN, NDIS }); w_in_0 = 0;
          end
        //   save lsb of west, out = west with carry shifted in right
        saved1 = w_out_0; do({ NMEM, RW, ZEROS, R2, SRC, CN, NDIS });
        //   put out into both in_1 and mem[2], west = r1
        do({ `M 2, OUT, T, F, T, R1, SRC, RW, ZEROS, CN, NDIS });
        //   both r1 and out = west with saved bit shifted in right
        w_in_0 = saved1; do({ NMEM, RW, SRC, R1, SRC, CN, NDIS });
        //   put out into mem[3], west = r0, clear out
        do({ `M 3, OUT, T, F, F, R0, SRC, RW, ZEROS, CN, NDIS });
      end

    if (negative)
      begin // negate result
        //   put mem[3] in in_2, clear out
        do({ `M 3, MEM, F, T, F, NALU, CN, NDIS });
        //   clear in_1, out = ~in_2
        do({ `M 0, OUT, F, F, T, R0, SRC, R0, NIN2, CN, NDIS });
        //   put out into in_2
        do({ `M 0, OUT, F, T, F, NALU, CN, NDIS });
        //   compute carry for in_1(=0) + in_2 + c(=1)
        do({ NMEM, NALU, C1, NDIS });
        //   out = in_1(=0) + in_2 + c(=1), put mem[2] in in_2
        do({ `M 2, MEM, F, T, F, RR, ZEROS, RR, SUM12S, CN, NDIS });
        //   put out in mem[3], out = ~in_2
        do({ `M 3, OUT, T, F, F, R0, SRC, R0, NIN2, CN, NDIS });
        //   put out into in_2
        do({ `M 0, OUT, F, T, F, NALU, CN, NDIS });
        //   compute carry for in_1(=0) + in_2 + c
        do({ NMEM, NALU, CC, NDIS });
        //   out = in_1(=0) + in_2 + c
        do({ NMEM, RR, ZEROS, RR, SUM12S, CN, NDIS });
        //   put out into mem[2]
        do({ `M 2, OUT, T, F, F, NALU, CN, NDIS });
      end
    else // positive
      //   do nothing (filler cycles)
      repeat (10) do({ NOOP });

    r_0_dump;
    m_0_dump;
    $display("unsigned:  %0d x %0d = %0d", pe_0.mem[0], pe_0.mem[1], 
             double * pe_0.mem[2] + pe_0.mem[3]);
    $display("%0d clock cycles", clock_ct);
  end

task reset_regs;
  begin
    #NS reset = 1;
    #NS reset = 0;
  end
endtask

task do;
  input [ADDR_WIDTH+34-1:0] i_0;
  begin
   instr_0 = i_0;
   #NS clock = 1;
   #NS clock = 0;
   clock_ct = clock_ct + 1;
  end
endtask

task r_0_dump;
  begin
    #NS dump_r_0 = 1;
    #NS dump_r_0 = 0;
  end
endtask

task m_0_dump;
  begin
    #NS dump_m_0 = 1;
    #NS dump_m_0 = 0;
  end
endtask

task form_feed;
  $write("\14");
endtask

task sign_stuff;
  if (flags_0[IN2_MSB_F]) // in_2 is negative
    begin  //  setup 2's complement of in_2
      // toggle negative result indicator, out = ~in_2
        negative = ~negative; do({ NMEM, R0, SRC, R0, NIN2, CN, NDIS });
      // in_2 = out
        do({ `M 0, OUT, F, T, F, NALU, CN, NDIS });
      // compute carry for in_1(=0) + in_2 + c(=1), clear out
        do({ NMEM, NALU, C1, NDIS });
    end
  else // in_2 is positive
    begin // setup for identity of in_2
      // filler cycle
        do({ NOOP });
      // filler cycle
        do({ NOOP });
      // compute carry for in_1(=0) + in_2 + c(=0), clear out
        do({ NMEM, NALU, C0, NDIS });
    end
endtask

endmodule

Host command: verilog
Command arguments:
    pe.v
    pc02-.v

VERILOG-XL 1.6a.4 log file created Jul 14, 1994  19:10:01
  * Copyright Cadence Design Systems, Inc. 1985, 1988.    *
  *     All Rights Reserved.       Licensed Software.     *
  * Confidential and proprietary information which is the *
  *      property of Cadence Design Systems, Inc.         *
Compiling source file "pe.v"

Compiling source file "pc02-.v"

Highest level modules:
pe0
pe2
pe3
pe4
pc2

2's-complement Integer 1x1=2-word Multiply with 1 PE
PE "PE_0" Reset, Clock Cycle # 0
PE "PE_0" Port and Register Dump # 0, Clock Cycle # 244
  PE_INSTR: mb_addr
            0010
            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  srce_reg  reg_res  dest_reg
               0        1         0         0        0000    10101010   0000
            out_res  carry  alu_dis  alu_dis_i  mb_dis  mb_dis_i  (p)
            00000000   00      0         0        0        0
     FLAGS: reg<0  reg=0  out<0  out=0  in2<0  in2=0  in1<0  in1=0
              0      0      0      1      1      0      0      1
            disab  carry  (r)
              0      0
       IN1: 00000000000000000000000000000000 (r)
       IN2: 11111111111111111111111111111111 (r)
       OUT: 00000000000000000000000000000000 (r)
        R0: 00000000000000000000000000000001 (r)
        R1: 00000000000000000000000000000001 (r)
        R2: 00000000000000000000000000000000 (r)
        R3: 00000000000000000000000000000000 (r)
        R4: 00000000000000000000000000000000 (r)
        R5: 00000000000000000000000000000000 (r)
        R6: 00000000000000000000000000000000 (r)
        R7: 00000000000000000000000000000000 (r)
        R8: 00000000000000000000000000000000 (r)
        R9: 00000000000000000000000000000000 (r)
   DISABLE: 00000000000000000000000000000000 (r)
    ROUTER: 00000000000000000000000000000000 (r)
      R_IN: 00000000000000000000000000000000 (p/r)
     NORTH: 00000000000000000000000000000000 (r)
      N_IN: 00000000000000000000000000000000 (p)
     SOUTH: 00000000000000000000000000000000 (r)
      S_IN: 00000000000000000000000000000000 (p)
      EAST: 00000000000000000000000000000000 (r)   E_IN: 0 (p)
      W_IN: 0 (p)   WEST: 00000000000000000000000000000001 (r)
PE "PE_0" Memory Dump # 0, Clock Clycle # 244
  0:  ffffffff 00000001 ffffffff ffffffff
  4:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  8:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  c:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
unsigned:  4294967295 x 1 = 18446744073709551615
244 clock cycles
36 warnings
34916 simulation events
CPU time: 1.3 secs to compile + 0.4 secs to link + 5.4 secs in simulation
End of VERILOG-XL 1.6a.4   Jul 14, 1994  19:10:08

module pc3;

// pc03-.v
// a Verilog-XL behavioral model of a reconfigurable processor configuration
// for a 2's-complement integer shift-add 1x1=1 word multiply with 1 PE
// (highest level module; requires module pe in file pe.v)
// for Dr. W. B. Ligon, E&CE dept., Clemson U., 1992-4
// by Ken Winiecki

//  system parameters:
`define    ADDR_WIDTH 4                //  width of PE memory address, in bits
parameter  WORD_WIDTH  = 32,           //  width of PE word, in bits
           MEM_LENGTH  = 16,           //  length of PE memory, in words
           MHZ         = 16.7,         //  clock speed, in "megahertz"
           NS          = 500/MHZ,      //  clock half-period, in "nanoseconds"
           ADDR_WIDTH  = `ADDR_WIDTH;  //  Had to use a "`define" above to 
                                       //  circumnavigate a Verilog-XL bug that
                                       //  prevents parameters from working as 
                                       //  bit length specifiers!!!

//  variable declarations:
reg clock, reset, w_in_0, dump_r_0, dump_m_0, negative, op_overflow, overflow;
reg [ADDR_WIDTH+34-1:0] instr_0;
wire e_out_0, w_out_0;
wire [9:0] flags_0;
integer clock_ct;

//  PE instances and connections:
pe pe_0 (clock, reset, instr_0, flags_0, 
         0,0,0,w_in_0,0, ,,e_out_0,w_out_0,, 0,,,,, dump_r_0, dump_m_0);

defparam  //  set PE-instance parameters to system parameters:
  pe_0.ADDR_WIDTH = ADDR_WIDTH,
  pe_0.WORD_WIDTH = WORD_WIDTH,
  pe_0.MEM_LENGTH = MEM_LENGTH,
  pe_0.PE_NAME    = "PE_0";

//  PE instruction fields and bit widths:
//    mb_addr    mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  src_reg  reg_res ...
//  (ADDR_WIDTH)    1        1         1         1         4        8
//    ...  dest_reg  out_res  carry  alu_dis  alu_dis_s  mb_dis  mb_dis_s
//            4         8       2       1         1        1        1

parameter  //  PE instruction field values:
//  mb_addr:   memory bus transfer address
//  mb_srce:   source of memory bus transfer is ...
  OUT = 1'b0,  //  ... register "OUT"
  MEM = 1'b1,  //  ... memory
//  mb_d_mem & mb_d_in2 & mb_d_in1:  destinations of memory bus transfers
  F = 1'b0,  //  false
  T = 1'b1,  //  true
//  srce_reg & dest_reg:  destination and source registers of ALU operations
  R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
  R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
  R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
  RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111,
//  reg_res & out_res:  ALU operands for "OUT" and destination register results
  IN1     = 8'b11110000, IN2     = 8'b11001100, SRC     = 8'b10101010,
  NIN1    = 8'b00001111, NIN2    = 8'b00110011, NSRC    = 8'b01010101,
  ZEROS   = 8'b00000000, ONES    = 8'b11111111,
  AND12   = 8'b11000000, OR12    = 8'b11111100, XOR12   = 8'b00111100,
  NAND12  = 8'b00111111, NOR12   = 8'b00000011, NXOR12  = 8'b11000011,
  AND1S   = 8'b10100000, OR1S    = 8'b11111010, XOR1S   = 8'b01011010,
  NAND1S  = 8'b01011111, NOR1S   = 8'b00000101, NXOR1S  = 8'b10100101,
  AND2S   = 8'b10001000, OR2S    = 8'b11101110, XOR2S   = 8'b01100110,
  NAND2S  = 8'b01110111, NOR2S   = 8'b00010001, NXOR2S  = 8'b10011001,
  AND12S  = 8'b10000000, OR12S   = 8'b11111110, XOR12S  = 8'b01111110,
  NAND12S = 8'b01111111, NOR12S  = 8'b00000001, NXOR12S = 8'b10000001,
  SUM12S  = 8'b10010110,
//  carry:
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN_1
  //  and IN_2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  CN = 2'b00,  //  do not compute carry (do an ALU operation)
  CC = 2'b01,  //  compute carry using carry flag for carry-in
  C0 = 2'b10,  //  compute carry using 0 for carry-in
  C1 = 2'b11;  //  compute carry using 1 for carry-in
//  alu_dis & mb_dis:      allow disabling of ALU/memory bus operation; T or F
//  alu_dis_i & mb_dis_i:  invert PE disable bit for ALU/memory bus op; T or F

//  convenience parameters and definitions for writing PE instructions:
`define M `ADDR_WIDTH'h  //  when specifying memory address (in hexidecimal)
parameter NMEM = { `M 0, MEM, F, F, F };  //  when not using memory bus
parameter NALU = { R0, SRC, R0, ZEROS };  //  when not doing ALU ops
                //  (note that flags are affected and OUT is cleared)
parameter NDIS = { F, F, F, F };  //  when not allowing any disabling
parameter NOOP = { NMEM, NALU, CN, NDIS };  //  when squandering clock cycles
                //  (note that flags are affected and OUT is cleared)

parameter // bit positions of PE flags
//  Note that flags other than carry are not affected by a carry operation,
//  and the carry flag is not affected by an ALU operation.
  REG_MSB_F = 9,  //  m.s.b. of destination register
  REG_ZER_F = 8,  //  if destination register = 0
  OUT_MSB_F = 7,  //  m.s.b. of register OUT
  OUT_ZER_F = 6,  //  if register OUT = 0
  IN2_MSB_F = 5,  //  m.s.b. of register IN_2
  IN2_ZER_F = 4,  //  if register IN_2 = 0
  IN1_MSB_F = 3,  //  m.s.b. of register IN_1
  IN1_ZER_F = 2,  //  if register IN_1 = 0
  DISABLE_F = 1,  //  state of PE disable bit
    CARRY_F = 0;  //  result of last carry operation


//  Write a program in Verilog-XL to control the processing elements directly,
//  and put it in the "initial" block to execute.  Set up the PE memory.
//  Reset the PE by clocking it's p_reset line.  (Clock a line using #NS to 
//  delay each transition.)  Build a PE instruction using the above defined 
//  instruction fields and value parameters.  Clock the PEs.  Monitor the 
//  flags of a PE using the above bit position parameters.  Note:  Verilog-XL 
//  has no way of dealing realistically with "don't cares," so never allow the 
//  use of "don't knows" (undefined values)!!!
initial 
  begin
    form_feed;
    $display("2's-complement Integer 1x1=1-word Multiply with 1 PE");
    w_in_0      = 0;
    dump_r_0    = 0;
    dump_m_0    = 0;
    clock       = 0;
    clock_ct    = 0;
    negative    = 0;
    op_overflow = 0;
    overflow    = 0;
    pe_0.mem[0] = 32'h1ffff;
    pe_0.mem[1] = 32'h10000;

    //   clear PE registers
    reset_regs;
    //   put mem[0] into in_2
    do({ `M 0, MEM, F, T, F, NALU, CN, NDIS });
    //   start adjusting for sign of in_2
    sign_stuff;
    //   west = in_1(=0) + in_2 + c, put mem[1] into in_2
    do({ `M 1, MEM, F, T, F, RR, SUM12S, RW, ZEROS, CN, NDIS });
    //   start adjusting for sign of in_2
    sign_stuff;
    //   east & out = in_1(=0) + in_2 + c
    do({ NMEM, RR, SUM12S, RE, SUM12S, CN, NDIS });

    repeat (WORD_WIDTH)
      begin
        //   put out into in_2, west = west rotated right, clear out
        w_in_0 = w_out_0;
        do({ `M 0, OUT, F, T, F, RW, SRC, RW, ZEROS, CN, NDIS });
        if (flags_0[REG_MSB_F]) // MSB of right-rotated operand is 1
          begin // compute new partial sum & carry
            //   compute carry for in_1 + in_2
            do({ NMEM, NALU, C0, NDIS });
            //   out = in_1 + in_2, clear in_2, check for overflow
            do({ `M 0, OUT, F, T, F, RR, ZEROS, RR, SUM12S, CN, NDIS });
            if (flags_0[CARRY_F] || op_overflow) overflow = 1;
          end
        else // MSB of right-rotated operand is 0
          begin // use previous partial sum & 0 carry
            //   filler cycle
            do({ NOOP });
            //   out = in_1, clear in_2;
            do({ `M 0, OUT, F, T, F, RR, ZEROS, RR, IN1, CN, NDIS });
          end
        //   check if next shifted operand will cause overflow if added,
        //   put out into in_1, east & out = east shifted left with zero
        if (e_out_0) op_overflow = 1;
        do({ `M 0, OUT, F, F, T, RE, SRC, RE, SRC, CN, NDIS });
      end

    if (negative)
      begin // negate result        
        //   out = ~in_1
        do({ NMEM, R0, SRC, R0, NIN1, CN, NDIS });
        //   put out into in_1
        do({ `M 0, OUT, F, F, T, NALU, CN, NDIS });
        //   compute carry for in_1 + in_2(=0) + c(=1)
        do({ NMEM, NALU, C1, NDIS });
        //   out = in_1 + in_2(=0) + c(=1)
        do({ NMEM, RR, ZEROS, RR, SUM12S, CN, NDIS });
      end
    else // positive
      begin // result identity
        //   do nothing (filler cycles)
        repeat (3) do({ NOOP });
        //   out = in_1
        do({ NMEM, R0, SRC, R0, IN1, CN, NDIS });
      end

    //   put out into mem[2]
    do({ `M 2, OUT, T, F, F, NALU, CN, NDIS });

    r_0_dump;
    m_0_dump;
    $display("unsigned:  %0d x %0d = %0d, overflow = %0d", pe_0.mem[0], 
             pe_0.mem[1], pe_0.mem[2], overflow);
    $display("%0d clock cycles", clock_ct);
  end

task reset_regs;
  begin
    #NS reset = 1;
    #NS reset = 0;
  end
endtask

task do;
  input [ADDR_WIDTH+34-1:0] i_0;
  begin
   instr_0 = i_0;
   #NS clock = 1;
   #NS clock = 0;
   clock_ct = clock_ct + 1;
  end
endtask

task r_0_dump;
  begin
    #NS dump_r_0 = 1;
    #NS dump_r_0 = 0;
  end
endtask

task m_0_dump;
  begin
    #NS dump_m_0 = 1;
    #NS dump_m_0 = 0;
  end
endtask

task form_feed;
  $write("\14");
endtask

task sign_stuff;
  if (flags_0[IN2_MSB_F]) // in_2 is negative
    begin // setup 2's complement of in_2
      //   toggle negative result indicator, out = ~in_2
      negative = ~negative; do({ NMEM, R0, SRC, R0, NIN2, CN, NDIS });
      //   in_2 = out
      do({ `M 0, OUT, F, T, F, NALU, CN, NDIS });
      //   compute carry for in_1(=0) + in_2 + c(=1), clear out
      do({ NMEM, NALU, C1, NDIS });
    end
  else // in_2 is positive
    begin // setup for identity of in_2
      //   filler cycle
      do({ NOOP });
      //   filler cycle
      do({ NOOP });
      //   compute carry for in_1(=0) + in_2 + c(=0), clear out
      do({ NMEM, NALU, C0, NDIS });
    end
endtask

endmodule

Host command: verilog
Command arguments:
    pe.v
    pc03-.v

VERILOG-XL 1.6a.4 log file created Jul 14, 1994  19:12:25
  * Copyright Cadence Design Systems, Inc. 1985, 1988.    *
  *     All Rights Reserved.       Licensed Software.     *
  * Confidential and proprietary information which is the *
  *      property of Cadence Design Systems, Inc.         *
Compiling source file "pe.v"

Compiling source file "pc03-.v"

Highest level modules:
pe0
pe2
pe3
pe4
pc3

2's-complement Integer 1x1=1-word Multiply with 1 PE
PE "PE_0" Reset, Clock Cycle # 0
PE "PE_0" Port and Register Dump # 0, Clock Cycle # 142
  PE_INSTR: mb_addr
            0010
            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  srce_reg  reg_res  dest_reg
               0        1         0         0        0000    10101010   0000
            out_res  carry  alu_dis  alu_dis_i  mb_dis  mb_dis_i  (p)
            00000000   00      0         0        0        0
     FLAGS: reg<0  reg=0  out<0  out=0  in2<0  in2=0  in1<0  in1=0
              0      1      0      1      0      1      1      0
            disab  carry  (r)
              0      0
       IN1: 11111111111111110000000000000000 (r)
       IN2: 00000000000000000000000000000000 (r)
       OUT: 00000000000000000000000000000000 (r)
        R0: 00000000000000000000000000000000 (r)
        R1: 00000000000000000000000000000000 (r)
        R2: 00000000000000000000000000000000 (r)
        R3: 00000000000000000000000000000000 (r)
        R4: 00000000000000000000000000000000 (r)
        R5: 00000000000000000000000000000000 (r)
        R6: 00000000000000000000000000000000 (r)
        R7: 00000000000000000000000000000000 (r)
        R8: 00000000000000000000000000000000 (r)
        R9: 00000000000000000000000000000000 (r)
   DISABLE: 00000000000000000000000000000000 (r)
    ROUTER: 00000000000000000000000000000000 (r)
      R_IN: 00000000000000000000000000000000 (p/r)
     NORTH: 00000000000000000000000000000000 (r)
      N_IN: 00000000000000000000000000000000 (p)
     SOUTH: 00000000000000000000000000000000 (r)
      S_IN: 00000000000000000000000000000000 (p)
      EAST: 00000000000000000000000000000000 (r)   E_IN: 0 (p)
      W_IN: 0 (p)   WEST: 00000000000000011111111111111111 (r)
PE "PE_0" Memory Dump # 0, Clock Clycle # 142
  0:  0001ffff 00010000 ffff0000 xxxxxxxx
  4:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  8:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
  c:  xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
unsigned:  131071 x 65536 = 4294901760, overflow = 1
142 clock cycles
36 warnings
19698 simulation events
CPU time: 1.3 secs to compile + 0.4 secs to link + 3.0 secs in simulation
End of VERILOG-XL 1.6a.4   Jul 14, 1994  19:12:29

module pc4;

// pc04-.v
// a Verilog-XL behavioral model of a reconfigurable processor configuration
// for a 2's-complement integer shift-add 1x1=1 word multiply with 2 PE's
// (highest level module; requires module pe in file pe.v)
// for Dr. W. B. Ligon, E&CE dept., Clemson U., 1992-4
// by Ken Winiecki

//  system parameters:
`define    ADDR_WIDTH 4                //  width of PE memory address, in bits
parameter  WORD_WIDTH  = 32,           //  width of PE word, in bits
           MEM_LENGTH  = 16,           //  length of PE memory, in words
           MHZ         = 16.7,         //  clock speed, in "megahertz"
           NS          = 500/MHZ,      //  clock half-period, in "nanoseconds"
           ADDR_WIDTH  = `ADDR_WIDTH;  //  Had to use a "`define" above to 
                                       //  circumnavigate a Verilog-XL bug that
                                       //  prevents parameters from working as 
                                       //  bit length specifiers!!!

//  variable declarations:
reg clock, reset,
    dump_r_0, dump_m_0,
    dump_r_1, dump_m_1,
    condition_0, condition_1, negative, op_ov_0, op_ov_1, overflow;
reg [ADDR_WIDTH+34-1:0] instr_0, instr_1;
wire e_out_0, w_0, e_out_1, w_1;
wire [9:0] flags_0, flags_1;
wire [WORD_WIDTH-1:0] s0_n1, n1_s0;
integer clock_ct;

//  PE instances and connections:
pe pe_0 (clock, reset, instr_0, flags_0, 
             0, n1_s0,       0, w_0, 0, 
              , s0_n1, e_out_0, w_0,  , 
         0,,,,, dump_r_0, dump_m_0);
pe pe_1 (clock, reset, instr_1, flags_1, 
         s0_n1,     0,       0, w_1, 0, 
         n1_s0,      , e_out_1, w_1,  , 
         0,,,,, dump_r_1, dump_m_1);

defparam  //  set PE-instance parameters to system parameters:
  pe_0.ADDR_WIDTH = ADDR_WIDTH,
  pe_0.WORD_WIDTH = WORD_WIDTH,
  pe_0.MEM_LENGTH = MEM_LENGTH,
  pe_0.PE_NAME    = "PE_0",
  pe_1.ADDR_WIDTH = ADDR_WIDTH,
  pe_1.WORD_WIDTH = WORD_WIDTH,
  pe_1.MEM_LENGTH = MEM_LENGTH,
  pe_1.PE_NAME    = "PE_1";

//  PE instruction fields and bit widths:
//    mb_addr    mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  src_reg  reg_res ...
//  (ADDR_WIDTH)    1        1         1         1         4        8
//    ...  dest_reg  out_res  carry  alu_dis  alu_dis_s  mb_dis  mb_dis_s
//            4         8       2       1         1        1        1

parameter  //  PE instruction field values:
//  mb_addr:   memory bus transfer address
//  mb_srce:   source of memory bus transfer is ...
  OUT = 1'b0,  //  ... register "OUT"
  MEM = 1'b1,  //  ... memory
//  mb_d_mem & mb_d_in2 & mb_d_in1:  destinations of memory bus transfers
  F = 1'b0,  //  false
  T = 1'b1,  //  true
//  srce_reg & dest_reg:  destination and source registers of ALU operations
  R0 = 4'b0000, R1 = 4'b0001, R2 = 4'b0010, R3 = 4'b0011,
  R4 = 4'b0100, R5 = 4'b0101, R6 = 4'b0110, R7 = 4'b0111,
  R8 = 4'b1000, R9 = 4'b1001, RD = 4'b1010, RR = 4'b1011,
  RN = 4'b1100, RS = 4'b1101, RE = 4'b1110, RW = 4'b1111,
//  reg_res & out_res:  ALU operands for "OUT" and destination register results
  IN1     = 8'b11110000, IN2     = 8'b11001100, SRC     = 8'b10101010,
  NIN1    = 8'b00001111, NIN2    = 8'b00110011, NSRC    = 8'b01010101,
  ZEROS   = 8'b00000000, ONES    = 8'b11111111,
  AND12   = 8'b11000000, OR12    = 8'b11111100, XOR12   = 8'b00111100,
  NAND12  = 8'b00111111, NOR12   = 8'b00000011, NXOR12  = 8'b11000011,
  AND1S   = 8'b10100000, OR1S    = 8'b11111010, XOR1S   = 8'b01011010,
  NAND1S  = 8'b01011111, NOR1S   = 8'b00000101, NXOR1S  = 8'b10100101,
  AND2S   = 8'b10001000, OR2S    = 8'b11101110, XOR2S   = 8'b01100110,
  NAND2S  = 8'b01110111, NOR2S   = 8'b00010001, NXOR2S  = 8'b10011001,
  AND12S  = 8'b10000000, OR12S   = 8'b11111110, XOR12S  = 8'b01111110,
  NAND12S = 8'b01111111, NOR12S  = 8'b00000001, NXOR12S = 8'b10000001,
  SUM12S  = 8'b10010110,
//  carry:
  //  Note:  The PE only does EITHER a carry operation OR an ALU operation in
  //  one instruction cycle.  A carry word is computed using registers IN_1
  //  and IN_2 and the specified carry-in, and is made available at the input
  //  from the router, r_in.  The carry-out is placed in the carry flag of the
  //  p_flags register.
  CN = 2'b00,  //  do not compute carry (do an ALU operation)
  CC = 2'b01,  //  compute carry using carry flag for carry-in
  C0 = 2'b10,  //  compute carry using 0 for carry-in
  C1 = 2'b11;  //  compute carry using 1 for carry-in
//  alu_dis & mb_dis:      allow disabling of ALU/memory bus operation; T or F
//  alu_dis_i & mb_dis_i:  invert PE disable bit for ALU/memory bus op; T or F

//  convenience parameters and definitions for writing PE instructions:
`define M `ADDR_WIDTH'h  //  when specifying memory address (in hexidecimal)
parameter NMEM = { `M 0, MEM, F, F, F };  //  when not using memory bus
parameter NALU = { R0, SRC, R0, ZEROS };  //  when not doing ALU ops
                //  (note that flags are affected and OUT is cleared)
parameter NDIS = { F, F, F, F };  //  when not allowing any disabling
parameter NOOP = { NMEM, NALU, CN, NDIS };  //  when squandering clock cycles
                //  (note that flags are affected and OUT is cleared)

parameter // bit positions of PE flags
//  Note that flags other than carry are not affected by a carry operation,
//  and the carry flag is not affected by an ALU operation.
  REG_MSB_F = 9,  //  m.s.b. of destination register
  REG_ZER_F = 8,  //  if destination register = 0
  OUT_MSB_F = 7,  //  m.s.b. of register OUT
  OUT_ZER_F = 6,  //  if register OUT = 0
  IN2_MSB_F = 5,  //  m.s.b. of register IN_2
  IN2_ZER_F = 4,  //  if register IN_2 = 0
  IN1_MSB_F = 3,  //  m.s.b. of register IN_1
  IN1_ZER_F = 2,  //  if register IN_1 = 0
  DISABLE_F = 1,  //  state of PE disable bit
    CARRY_F = 0;  //  result of last carry operation


//  Write a program in Verilog-XL to control the processing elements directly,
//  and put it in the "initial" block to execute.  Set up the PE memory.
//  Reset the PE by clocking it's p_reset line.  (Clock a line using #NS to 
//  delay each transition.)  Build a PE instruction using the above defined 
//  instruction fields and value parameters.  Clock the PEs.  Monitor the 
//  flags of a PE using the above bit position parameters.  Note:  Verilog-XL 
//  has no way of dealing realistically with "don't cares," so never allow the 
//  use of "don't knows" (undefined values)!!!
initial 
  begin
    form_feed;
    $display("2's-complement Integer 1x1=1-word Multiply with 2 PE's");
    clock       = 0;
    clock_ct    = 0;
    dump_r_0    = 0;
    dump_m_0    = 0;
    dump_r_1    = 0;
    dump_m_1    = 0;
    pe_0.mem[0] = 32'h1ffff;
    pe_0.mem[1] = 32'h10000;
    pe_1.mem[0] = pe_0.mem[0];
    pe_1.mem[1] = pe_0.mem[1];

    // both:  clear all registers
    reset_regs;

    // 0: mem[0] -> in_2
    // 1: mem[1] -> in_2
    instr_0 = { `M 0, MEM, F, T, F, NALU, CN, NDIS };
    instr_1 = { `M 1, MEM, F, T, F, NALU, CN, NDIS };
    clockem;

    // both:  if in_2 negative, then out = ~in_2, in_2 = out, compute carry for
    //        in_2 + 1; otherwise in_2 positive, so compute carry for in_2 + 0
    if (flags_0[IN2_MSB_F]) condition_0 = 1;
    else                    condition_0 = 0;
    if (flags_1[IN2_MSB_F]) condition_1 = 1;
    else                    condition_1 = 0;
    if (condition_0^condition_1) negative = 1;
    else                         negative = 0;
    if (condition_0) instr_0 = { NMEM, R0, SRC, R0, NIN2, CN, NDIS };
    else             instr_0 = { NOOP };
    if (condition_1) instr_1 = { NMEM, R0, SRC, R0, NIN2, CN, NDIS };
    else             instr_1 = { NOOP };
    clockem;
    if (condition_0) instr_0 = { `M 0, OUT, F, T, F, NALU, CN, NDIS };
    else             instr_0 = { NOOP };
    if (condition_1) instr_1 = { `M 0, OUT, F, T, F, NALU, CN, NDIS };
    else             instr_1 = { NOOP };
    clockem;
    if (condition_0) instr_0 = { NMEM, NALU, C1, NDIS };
    else             instr_0 = { NMEM, NALU, C0, NDIS };
    if (condition_1) instr_1 = { NMEM, NALU, C1, NDIS };
    else             instr_1 = { NMEM, NALU, C0, NDIS };
    clockem;

    // 0: south & out = in_2 + c
    // 1: north & out = in_2 + c
    instr_0 = { NMEM, RR, SUM12S, RS, SUM12S, CN, NDIS };
    instr_1 = { NMEM, RR, SUM12S, RN, SUM12S, CN, NDIS };
    clockem;

    // 0: out -> in_2, east = south
    // 1: out -> in_2, west = north
    instr_0 = { `M 0, OUT, F, T, F, RS, SRC, RE, ZEROS, CN, NDIS };
    instr_1 = { `M 0, OUT, F, T, F, RN, SRC, RW, ZEROS, CN, NDIS };
    clockem;

    // 0: west = in_2
    // 1: east = in_2
    instr_0 = { NMEM, R0, IN2, RW, ZEROS, CN, NDIS };
    instr_1 = { NMEM, R0, IN2, RE, ZEROS, CN, NDIS };
    clockem;

    // 0: west = west rotated right
    // 1: do nothing
    instr_0 = { NMEM, RW, SRC, RW, ZEROS, CN, NDIS };
    instr_1 = { NOOP };
    clockem;

    // 0: check for upcoming overflow possibility, 
    //    east & out = east shifted left with 0
    // 1: out = in_2
    if (e_out_0) op_ov_0 = 1;
    else op_ov_0 = 0;
    instr_0 = { NMEM, RE, SRC, RE, SRC, CN, NDIS };
    instr_1 = { NMEM, R0, ZEROS, R0, IN2, CN, NDIS };
    clockem;

    op_ov_1     = 0;
    overflow    = 0;
    repeat (WORD_WIDTH/2)
      begin

        // both:  out -> in_2, west = west rotated right, clear out
        instr_0 = { `M 0, OUT, F, T, F, RW, SRC, RW, ZEROS, CN, NDIS };
        instr_1 = { `M 0, OUT, F, T, F, RW, SRC, RW, ZEROS, CN, NDIS };
        clockem;

        // 0: if op bit = 1, compute carry for in_1 + in_2, south & out
        //    = in_1 + in_2, check overflow; otherwise, south & out = in_1
        // 1: if op bit = 1, compute carry for in_1 + in_2, north & out
        //    = in_1 + in_2, check overflow; otherwise, north & out = in_1
        if (flags_0[REG_MSB_F]) condition_0 = 1;
        else                    condition_0 = 0;
        if (flags_1[REG_MSB_F]) condition_1 = 1;
        else                    condition_1 = 0;
        if (condition_0) instr_0 = { NMEM, NALU, C0, NDIS };
        else             instr_0 = { NOOP };
        if (condition_1) instr_1 = { NMEM, NALU, C0, NDIS };
        else             instr_1 = { NOOP };
        clockem;
        if (condition_0)
             instr_0 = { NMEM, RR, SUM12S, RS, SUM12S, CN, NDIS };
        else instr_0 = { NMEM, RR, IN1, RS, IN1, CN, NDIS };
        if (condition_1) 
             instr_1 = { NMEM, RR, SUM12S, RN, SUM12S, CN, NDIS };
        else instr_1 = { NMEM, RR, IN1, RN, IN1, CN, NDIS };
        clockem;
        if ( condition_0 && (flags_0[CARRY_F] || op_ov_0)
          || condition_1 && (flags_1[CARRY_F] || op_ov_1) ) overflow = 1;

        // both:  out -> in_1, west = west rotated right
        instr_0 = { `M 0, OUT, F, F, T, RW, SRC, RW, ZEROS, CN, NDIS };
        instr_1 = { `M 0, OUT, F, F, T, RW, SRC, RW, ZEROS, CN, NDIS };
        clockem;

        // both:  east = east shifted left with zero
        instr_0 = { NMEM, RE, SRC, RE, ZEROS, CN, NDIS };
        instr_1 = { NMEM, RE, SRC, RE, ZEROS, CN, NDIS };
        clockem;

        // both:  check for upcoming overflow possibility,
        //        east & out = east shifted left with zero
        if (e_out_0) op_ov_0 = 1;
        if (e_out_1) op_ov_1 = 1;
        instr_0 = { NMEM, RE, SRC, RE, SRC, CN, NDIS };
        instr_1 = { NMEM, RE, SRC, RE, SRC, CN, NDIS };
        clockem;

      end

    // 0: out = south
    // 1: out = north
    instr_0 = { NMEM, RS, ZEROS, R0, SRC, CN, NDIS };
    instr_1 = { NMEM, RN, ZEROS, R0, SRC, CN, NDIS };
    clockem;

    // both:  out -> in_2, clear out
    instr_0 = { `M 0, OUT, F, T, F, NALU, CN, NDIS };
    instr_1 = { `M 0, OUT, F, T, F, NALU, CN, NDIS };
    clockem;

    // both:  compute carry for in_1 + in_2
    instr_0 = { NMEM, NALU, C0, NDIS };
    instr_1 = { NMEM, NALU, C0, NDIS };
    clockem;

    // both:  out = in_1 + in_2, clear in_2, check overflow
    instr_0 = { `M 0, OUT, F, T, F, RR, ZEROS, R0, SUM12S, CN, NDIS };
    instr_1 = { `M 0, OUT, F, T, F, RR, ZEROS, R0, SUM12S, CN, NDIS };
    clockem;
    if (flags_0[CARRY_F] || flags_1[CARRY_F]) overflow = 1;

    if (negative)
      begin // negate and save result

        // both:  out -> in_1
        instr_0 = { `M 0, OUT, F, F, T, NALU, CN, NDIS };
        instr_1 = { `M 0, OUT, F, F, T, NALU, CN, NDIS };
        clockem;

        // both:  out = ~in_1
        instr_0 = { NMEM, R0, SRC, R0, NIN1, CN, NDIS };
        instr_1 = { NMEM, R0, SRC, R0, NIN1, CN, NDIS };
        clockem;

        // both:  out -> in_1
        instr_0 = { `M 0, OUT, F, F, T, NALU, CN, NDIS };
        instr_1 = { `M 0, OUT, F, F, T, NALU, CN, NDIS };
        clockem;

        // both:  compute carry for in_1 + 1
        instr_0 = { NMEM, NALU, C1, NDIS };
        instr_1 = { NMEM, NALU, C1, NDIS };
        clockem;

        // both:  out = in_1 + c
        instr_0 = { NMEM, RR, ZEROS, R0, SUM12S, CN, NDIS };
        instr_1 = { NMEM, RR, ZEROS, R0, SUM12S, CN, NDIS };
        clockem;

        // both:  out -> mem[2]
        instr_0 = { `M 2, OUT, T, F, F, NALU, CN, NDIS };
        instr_1 = { `M 2, OUT, T, F, F, NALU, CN, NDIS };
        clockem;

      end
    else // positive
      begin // save result

        // both:  out -> mem[2]
        instr_0 = { `M 2, OUT, T, F, F, NALU, CN, NDIS };
        instr_1 = { `M 2, OUT, T, F, F, NALU, CN, NDIS };
        clockem;

        // both:  do nothing
        repeat (5)
          begin
            instr_0 = { NOOP };
            instr_1 = { NOOP };
            clockem;
          end

      end

    r_0_dump;
    m_0_dump;
    $display("unsigned:  %0d x %0d = %0d, overflow = %0d", pe_0.mem[0], 
             pe_0.mem[1], pe_0.mem[2], overflow);
    form_feed;
    r_1_dump;
    m_1_dump;
    $display("unsigned:  %0d x %0d = %0d, overflow = %0d", pe_1.mem[0], 
             pe_1.mem[1], pe_1.mem[2], overflow);
    $display("%0d clock cycles", clock_ct);
  end

task reset_regs;
  begin
    #NS reset = 1;
    #NS reset = 0;
  end
endtask

task clockem;
  begin
   #NS clock = 1;
   #NS clock = 0;
   clock_ct = clock_ct + 1;
  end
endtask

task r_0_dump;
  begin
    #NS dump_r_0 = 1;
    #NS dump_r_0 = 0;
  end
endtask

task m_0_dump;
  begin
    #NS dump_m_0 = 1;
    #NS dump_m_0 = 0;
  end
endtask

task r_1_dump;
  begin
    #NS dump_r_1 = 1;
    #NS dump_r_1 = 0;
  end
endtask

task m_1_dump;
  begin
    #NS dump_m_1 = 1;
    #NS dump_m_1 = 0;
  end
endtask

task form_feed;
  $write("\14");
endtask

endmodule

Host command: verilog
Command arguments:
    pe.v
    pc04-.v

VERILOG-XL 1.6a.4 log file created Jul 14, 1994  19:13:20
  * Copyright Cadence Design Systems, Inc. 1985, 1988.    *
  *     All Rights Reserved.       Licensed Software.     *
  * Confidential and proprietary information which is the *
  *      property of Cadence Design Systems, Inc.         *
Compiling source file "pe.v"

Compiling source file "pc04-.v"

Highest level modules:
pe0
pe2
pe3
pe4
pc4

2's-complement Integer 1x1=1-word Multiply with 2 PE's
PE "PE_1" Reset, Clock Cycle # 0
PE "PE_0" Reset, Clock Cycle # 0
PE "PE_0" Port and Register Dump # 0, Clock Cycle # 115
  PE_INSTR: mb_addr
            0000
            mb_srce  mb_d_mem  mb_d_in2  mb_d_in1  srce_reg  reg_res  dest_reg
               1        0         0         0        0000    10101010   0000
            out_res  carry  alu_dis  alu_dis_